Verification Engineer
2 months ago
Role : Verification Engineer
Exp : 7+yrs
Location : Bangalore/Chennai
Job Description :
Mandatory Skill : System Verilog,UVM
- Proficient in System Verilog and UVM.
- Strong knowledge of verification methodologies.
- Experience with simulation and debugging tools.
Responsibilities :
- Meeting with product designers to determine functionality protocols.
- Reviewing the product designs and noting likely points of failure.
- Designing verification methodology based on product designs and failure points.
- Determining testing environments and verification tools.
- Reviewing existing engineering criteria for similar products.
- Building and calibrating electrical instruments and testing tools.
- Planning the method of sequence for testing operations.
- Instituting and tweaking testing mechanisms and protocols.
- Conducting quality control inspections.
- Writing up final test procedures and training QC staff.
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