Staff Engineer, Design Verification Engineer

4 months ago

Bengaluru, India Analog Devices Full time

B.Tech/M.Tech with 8+ years of industry experience in Digital Pre-Silicon verification of RF/Bluetooth Modules. Good understanding of RF/Bluetooth Digital & Analog architectures. Exposure to products that integrate a wide variety of RF/Bluetooth related wireless modules. Good Knowledge of scenarios involving Digital-Analog interactions in RF/Bluetooth modules. Exposure & understanding of Analog/RF blocks & associated Behavioral Real Number models. Demonstrated experience of verification plan, verification environment development using UVM and verification/debug of complex products involving RF/Bluetooth modules. Experience in closing the verification of block, subsystem level verification using industry standard metrics like code and functional coverage is a must. Power aware verification with UPF, Power analysis and Power optimization. Gate level Simulation with timing annotated Assertion and formal knowledge are an advantage. Formal verification, define formal verification flow, connectivity and functional verification using formal tools. Experience and debug with digital simulators such as Cadence Xcelium/Synopsys VCS. Tracking of verification metrics and regression management, Metric Driven Verification (MDV) framework using tools such as Cadence vManager. System Verilog, C/C++, System C, TCL/Python/shell-scripting Exceptional interpersonal and communication skills, collaborate and influence innovative design development/verification methodologies to wider team spread across the globe. Quick to adopt new technologies with good problem-solving skills. Self-motivated and enthusiastic. All aspects of Digital Verification right from verification planning to test bench development to constraint random stimulus creation to score boarding to coverage closure. Come up with verification strategy for a Bluetooth Module at IP & SOC level after going through IP/Product requirements and design specifications. Defining verification plans, tests scenarios and verification methodology for IP and SOC level verification. Working with the digital/analog design team in generating and reviewing verification plans and closure of code and functional coverage. Deploy industry standard UVM based verification approach. UVM testbench architecture development and implementation of DV flows, methodology. Develop self-checking testcases. Collaborate and work closely with team members from various disciplines (system architects, digital design, analog design, AMS DV etc.) for first pass silicon. Formal verification of IP’s and Subsystems Support test and characterization teams in post-silicon validation. Collaborate with CAD team to deploy next generation innovative design verification methodologies to reduce overall TTM. Mentor junior engineers. Job Req Type: ExperiencedRequired Travel: Yes, 10% of the timeShift Type: 1st Shift/Days

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