Senior Staff Design Verification Engineer
4 days ago
Job Summary:
We are seeking a talented Senior Staff Design Verification Engineer to join our team at Renesas Electronics. As a key member of our design verification team, you will be responsible for developing and implementing verification testbenches for complex integrated circuits.
Key Responsibilities:
- Develop verification testbench components for chip/module level using System Verilog, C & Perl.
- Use high-level concepts (Object-oriented, UVM, etc) to develop an extendable environment.
- Define and execute detailed verification plans from spec working with architects, designers, system engineers.
- Incorporate code coverage, functional coverage, assertions, cover groups, etc to achieve 100% verification completeness prior to tape-out.
- Debug tests, run gate-level simulations.
- Develop automated/scripted design flows for the above-mentioned development processes.
- Participate in silicon debug and analysis.
- Support generation of production test vectors.
Requirements:
- MS in Computer or Electrical Engineering with a minimum of 9+ years of experience in design/verification management of highly complex projects.
- Organized and creative thinker, motivated, and independent learner who can multitask in a dynamic environment, able to create and implement new solutions where required.
- Must be good in building verification environments preferably using the verification subset of high-level languages like System Verilog (OVM, UVM).
- Must be proficient in Verilog (System Verilog preferred).
- Understanding or prior experience with Industry standard protocols like DDR4/DDR5 is preferred.
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