Sr Principal Layout Engg

4 weeks ago

Bengaluru, India Onsemi Full time

Responsibilities : 

OnSemi is seeking a Senior Principal Analog Layout Engineer, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products including DC-DC PMIC/POL, Multiphase controllers, Dr. MOS, AC-DC converters, LED drivers, SiC drivers, Switches and e-fuses for consumer, industrial and automotive applications. In this role, you will focus on the following

Produce high quality layout for complex AMS IP blocks (voltage regulators, bandgap, current sense-amp, amplifier, high voltage switches, drivers etc)

Able to lead a team of 4-6 engg to develop complex block layout or full chip layout Review the work of team, take ownership of quality and driver towards continuous quality improvements Estimate the schedule, manpower resources and layout activity planning, responsible for meeting the schedule  Contribute to area estimation and optimization, floor planning, power routing, shielding, physical verification (DRC, ERC, LVS, ESD, , as well power analysis (EM / IR-Drop) Contribute and support team in taping out high-performance microcontroller chip Actively seek out opportunities to work with cross-functional teams (Chip team, Tech, CAD) Develop scripts and methods for layout design automation

#LI-RG1

Minimum Requirements

BS in Electrical Engineering or related + 12 years of experience, or MS + 10 years of experience preferred with experience in analog/mixed-signal layout design of deep submicron CMOS and BCD technologies

Qualification

Experience in delivering high quality analog layout IPs Good understanding of layout fundamentals and best practices Proficiency in interpretation of CALIBRE DRC, ERC, LVS, reports Programming knowledge in SKILL, Perl, and/or Python is a bonus Experience with CADENCE or MENTOR GRAPHICS layout tools Solid understanding of semiconductor manufacturing process and DFM techniques Proficient at debugging/fixing LVS/DRC errors Must be familiar with Cadence Design Environment (CDE) and Unix OS Must have strong communication skills and be a team player

#LI-RG1

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