Senior/Staff Engineer, CAD PDK PCell Dev

6 months ago

Hyderabad, India Micron Full time

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

JR45176 Senior/Staff Engineer, CAD PDK PCell Dev

Our vision is to transform how the world uses information to enrich life.

Join an inclusive team focused on one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solution we create help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while contributing to integrity, sustainability, and giving back to our communities. Because doing so can spark the very innovation we are pursuing.


Job Description:

As a Scribe CAD Senior/ Staff Engineer at Micron Technology, Inc., you will be enabling and deploying layout automation concepts to enhance memory design team's productivity. You will be collaborating with multiple global teams like CAD, Memory design, and Technology development teams.

Responsibilities and Tasks include, but not limited to:

Work closely with memory design and technology development teams and resolve their daily challenges and develop comprehensive solutions for future. Proactively identify problem areas for improvement, propose, and develop innovative solutions. Continuously evaluate and implement new tools and technologies to improve the current automation flows.  Demonstrate growth mindset and work towards submitting patent disclosures and research papers. Provide guidance and mentorship to junior members of the team.


  Qualifications: Minimum 5+ Years Experience on CAD PDK/PCell Development

Advanced understanding of PDK development/validation, EDA tools and CAD flows. Develop and enable programmatically defined P-cell (Parameterized layout generator) devices for memory layout modules. Implement advanced methodologies for layout automation which can be scalable between technologies and enhance design workflow. Good understanding of programming fundamentals, as well as exposure to various programming languages including: Skill/Skill++ (Cadence), Perl, Python, Tcl. Experience of developing physical verification collaterals using SVRF. Working experience of Physical Verification flow and analyzing/debugging DRC, ERC, LVS, DFM, Antenna and rule deck issues. Good understanding of basic CMOS process manufacturing and layout design rules. Working knowledge of Linux is a must. Excellent problem-solving skills with attention to detail.  Ability to work in a dynamic environment. Proficiency in working effectively with global teams and stakeholders

Education:

A Bachelor’s or Master’s degree in Computer Science, Computer Engineering, Electrical Engineering or Electronics Engineering.

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