Design Engineer

Position Description: Exp: 7-12 Yrs · Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure. · The candidate will have the opportunity to work on many varieties of...

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Location : Pune Design Engineer II Experience in developing complex test bench in System Verilog using OVM/UVM methodology Experience in coding functional coverage and system verilog assertions. Experience validation of...

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Location : Pune  Design Engineer II Experience in developing complex test bench in System Verilog using OVM/UVM methodology Experience in coding functional coverage and system verilog assertions. Experience validation of protocols such...

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Location : Pune  Design Engineer II Experience in developing complex test bench in System Verilog using OVM/UVM methodology Experience in coding functional coverage and system verilog assertions. Experience validation of protocols such...

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Position RequirementsM.S. or BTech Electrical/Computer/Electronics Engineering (or similar degree)Experience : 3+ years sound knowledge of DDR4/5, LPDDR4/5 IP. Hands on design/verification experience on DDR protocol Exposure to...

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Position RequirementsM.S. or BTech Electrical/Computer/Electronics Engineering (or similar degree)Experience : 3+ years sound knowledge of DDR4/5, LPDDR4/5 IP. Hands on design/verification experience on DDR protocol Exposure to DDR...

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Position RequirementsM.S. or BTech Electrical/Computer/Electronics Engineering (or similar degree)Experience : 3+ years sound knowledge of DDR4/5, LPDDR4/5 IP. Hands on design/verification experience on DDR protocol Exposure to DDR...

Position Description:Exp: 7-12 Yrs· Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.· The candidate will have the opportunity to work on many varieties of challenging...

Position Description:Exp: 7-12 Yrs· Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.· The candidate will have the opportunity to work on many varieties of challenging...

Position Description: Exp: 7-12 Yrs · Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure. · The candidate will have the opportunity to work on many varieties of...

Position Description: Exp: 7-12 Yrs · Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.· The candidate will have the opportunity to work on many varieties of...

Position Description: Exp: 7-12 Yrs · Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.· The candidate will have the opportunity to work on many varieties of...

Position Description: Exp: 7-12 Yrs · Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.· The candidate will have the opportunity to work on many varieties of...

Job Responsibilities:Development, automation and maintenance of EDA flows and scripts for physical implementationPPA characterization and optimization of flow for performance-oriented and power-oriented best-in-class IP cores in advanced process nodes, such as 7nm/5nm/3nm/2nmManage regression infrastructure that tracks quality of the RTL/flow development as...

Job Responsibilities: Development, automation and maintenance of EDA flows and scripts for physical implementation PPA characterization and optimization of flow for performance-oriented and power-oriented best-in-class IP cores in advanced process nodes, such as 7nm/5nm/3nm/2nm Manage regression infrastructure that tracks quality of the RTL/flow development...

Job Responsibilities:Development, automation and maintenance of EDA flows and scripts for physical implementationPPA characterization and optimization of flow for performance-oriented and power-oriented best-in-class IP cores in advanced process nodes, such as 7nm/5nm/3nm/2nmManage regression infrastructure that tracks quality of the RTL/flow development as...

Experience in developing complex test bench in System Verilog using OVM/UVM methodologyExperience in coding functional coverage and system verilog assertions.Experience validation of protocols such as AXI4, AHB, functionality like DMA (Direct Memory Access Controllers), Arbiters.Knowledge of computer architecture, AI accelerators is a big plus.Well versed...

Experience in developing complex test bench in System Verilog using OVM/UVM methodologyExperience in coding functional coverage and system verilog assertions.Experience validation of protocols such as AXI4, AHB, functionality like DMA (Direct Memory Access Controllers), Arbiters.Knowledge of computer architecture, AI accelerators is a big plus.Well versed...

**Location**: Pune **Designation**: Junior Designer **Job Type**: 10AM - 7PM/Full Time **Salary**: 12k to 16k depends upon interview performance **Qualification**: B.Arch, B.Design (Diploma), B.E.Civil, Interior Designer **Experience**: 0 to 2 years experience, freshers preferred **Roles and Responsibilities** As Junior Designer, you will be working...

Position Description: Exp: 7-12 Yrs · Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.· The candidate will have the opportunity to work on many varieties of...