SoC Physical Design Engineer

JD: JD: Lead with experience in SoC Physical design across multiple technology nodes including 5nm for TSMC & Other foundries. Excellent hands-on P&R skills with expert knowledge in ICC/Innovus Expert knowledge in all aspects of PD from Synthesis to GDSII, Strong background in Floorplanning, Placement, CTS, Routing, P&R, Extraction, IR Drop Analysis, Timing,...

JD: JD:Lead with experience in SoC Physical design across multiple technology nodes including 5nm for TSMC & Other foundries.Excellent hands-on P&R skills with expert knowledge in ICC/InnovusExpert knowledge in all aspects of PD from Synthesis to GDSII, Strong background in Floorplanning, Placement, CTS, Routing, P&R, Extraction, IR Drop Analysis, Timing,...

Location: Bangalore, Hyderabad, Noida, and Coimbatore.Skills:Soc level floorplanning, partitioning, timing budget generations, power planning, SOC PnR, CTS, block integrationHandling timing closure of high frequency blocks.Expertise in signoff closure Timing with SI and OCV, Power, IR and physical verification at both block and chip level.Understanding...

JD: JD: Lead with experience in SoC Physical design across multiple technology nodes including 5nm for TSMC & Other foundries.Excellent hands-on P&R skills with expert knowledge in ICC/InnovusExpert knowledge in all aspects of PD from Synthesis to GDSII, Strong background in Floorplanning, Placement, CTS, Routing, P&R, Extraction, IR Drop Analysis, Timing,...

SoC Design EngineerJob Title: SoC Design Engineer Experience: 2 - 5 years Education: M.Tech or B.Tech in EE/ECEResponsibilities:SoC-level integration of IPs, interconnects, memory subsystemsDefine SoC microarchitecture and collaborate with system architectsAddress performance, power, and area trade-offsCollaborate with verification, software, and physical...

Job DetailsJob Description:Performs physical design implementation of CPU designs from RTL to GDS to create a design database that is ready for manufacturing.Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power...

JD: JD: - Lead with experience in SoC Physical design across multiple technology nodes including 5nm for TSMC & Other foundries. - Excellent hands-on P&R skills with expert knowledge in ICC/Innovus - Expert knowledge in all aspects of PD from Synthesis to GDSII, Strong background in Floorplanning, Placement, CTS, Routing, P&R, Extraction, IR Drop Analysis,...

Performs physical design implementation of CPU designs from RTL to GDS to create a design database that is ready for manufacturing.Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.Conducts...

Positions are open for full-time SOC physical implementation from unit level to chip level, involving all aspects of physical design functions such as P&R, timing, floorplan, clocking, electrical analysis, and power. ResponsibilitiesOwn block level design from RTL-to-GDSII and drive synthesis, floor-planning, place & route, timing closure, and signoff.Work...

3+ years relevant experience Lead with experience in SoC Physical design across multiple technology nodes including 5nm for TSMC & Other foundries. Excellent hands-on P&R skills with expert knowledge in ICC/Innovus Expert knowledge in all aspects of PD from Synthesis to GDSII, Strong background in Floorplanning, Placement, CTS, Routing, P&R, Extraction, IR...