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FPGA RTL Design Engineer

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Bengaluru, Karnataka, India NXP Semiconductors Full time ₹ 15,00,000 - ₹ 25,00,000 per year

Company Description

NXP Semiconductors N.V. (NASDAQ: NXPI) is a trusted partner for innovative solutions in the automotive, industrial & IoT, mobile, and communications infrastructure markets. The company combines leading-edge technology with pioneering people to develop solutions that make the connected world better, safer, and more secure. With operations in over 30 countries and a revenue of $12.61 billion in 2024, NXP focuses on creating a sustainable and inclusive work environment. NXP offers career development opportunities through both online and offline learning to help you grow professionally. Find out more at

Role Description (Contractor role for NXP)

This is a full-time hybrid role for an FPGA RTL Design Engineer located in Bengaluru with some acceptable work from home days. The FPGA RTL Design Engineer will be responsible for designing SOC RTL to FPGA , testing, and debugging FPGA-based systems . Day-to-day tasks include creating RTL designs, verifying through simulation, and collaborating with cross-functional teams to ensure the design meets the required specifications and performance benchmarks.

Qualifications

  1. FPGA Architecture Knowledge

  2. The candidate should be familiar with FPGA architecture concepts such as:

  3. Logic Cells, CLBs, Slices

  4. MMCM
  5. IO Standards

  6. BRAM

  7. Hands-on Experience with Verilog & VHDL

  8. The candidate should have practical experience in writing RTL logic for (
    Not necessary with these all things but at least 3 to 4 areas should be Experienced
    ):

  9. Serial peripherals (e.g., I2C, I3C, SPI, UART, CAN).

  10. Image or video processing.
  11. Data scaling & grabbing in FPGA.
  12. High speed ADC data handling.
  13. External sensor configuration (e.g., cameras, antennas, analog & digital sensors).

  14. AXI or Avalon bus mapping with custom RTL.

  15. FPGA Timing Closure Expertise

  16. Strong experience in achieving timing closure for designs with high logic utilization FPGA's.
  17. RTL Testbench Development
  18. Experience in creating testbenches for FPGA RTL designs.

  19. Should have experience with below area's

  20. Zynq ARM A9 or A53 or MicroBlaze interface with external data's at RTL level (
    Not an FPGA IP's
    ).

  21. Clear understanding of synthesizable vs. non-synthesizable RTL constructs.
  22. Interfacing SERDES IPs like Aurora is plus.
  23. Should have RTL design experience with 16nm or smaller FPGA technologies (e.g.,
    Kintex, Virtex, Zynq Ultrascale
    +).

  24. CPU boot flow (Zynq) is plus.

  25. Debugging Skills

  26. Mandatory experience with debugging tools such as ILA, Signal Tap, and oscilloscopes.
  27. Linux Environment Experience
  28. Familiarity with Ubuntu or Red Hat Linux environments is a plus.

Please forward your resume to ""