DFT Engineer

Job Title: DFT Engineer (Design-for-Test)Experience:8–10 YearsLocation:NoidaEmployment Type:Full-TimeRole Overview:We are looking for ahighly skilled DFT (Design-for-Test) Engineerhands-on experiencein SoC DFT implementation and verification. The ideal candidate will have deep expertise inscan architectures, JTAG, boundary scan, memory BIST, ATPG, and...

The engineer needs to have hands-on experience in scan insertion,JTAG, LBIST, ATPG DRC & coverage analysis,Simulation debug with timing/SDF and post silicon debug.Looking only for 5+ years of experience in DFTHealth insuranceProvident fund

General Summary:As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits,...

System on Chip ,DFT implementation and verification of scan architectures, Joint Test Action Group, boundary ,Built-In Self-Test, Automatic Test Pattern Generation and LBIST ,Verilog/VHDL RTL coding , scan insertion ,DRCContact-

Role & responsibilitiesPreferred candidate profileThe candidate is expected to have clear understanding of BSCAN, MBIST, SCAN, ATPG and Simulation concepts.He/she must be hands-on with MBIST insertion, Scan Insertion, ATPG pattern generation and simulations, MBIST and BSCAN simulations using industry standard tools of Cadence/Siemens Tessent/Synopsys.Must...

Company:Qualcomm India Private LimitedJob Area:Engineering Group, Engineering Group > Hardware EngineeringGeneral Summary:As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware...

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.Design and implement DFT IP w/ Verilog/SystemVerilog and/or VHDLDesign and implement RTL for DFT IP incl. POST, ISTDevelop synthesis automation for DFT IP including synthesis and timing constraints, RTL insertion and verificationOwn and maintain,...

General Summary:As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with...

block-level timing constraints ,functional and DFT modes,STA analysis and closure ,PrimeTime,PT-ECO ,QoR,constraints validation,Front-End Design,DFT teams,Clock Tree Synthesis,Timing ECOs,TCL, Unix shell scripting Contact-

Position:Senior Engineer (Level 1)Job Description:Principal Accountabilities* Responsible for  floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, signal integrity, physical verification and DFM.* Execute block level place and route assignments from Netlist through...