VotaryTech - Senior Design Verification Engineer - UVM/System Verilog

Job OverviewWe are seeking an experienced and highly skilled Senior SOC Design Verification Engineer with a minimum of 5 years of hands-on experience in SOC Design Verification. As a key member of our team, you will play a pivotal role in ensuring the robustness and correctness of our cutting-edge System on Chip designs.Job DescriptionLead and manage SOC...

BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer.5+ years of Design Verification experience with SV/UVMStrong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.Design Verification experience verifying complex designs and...

Design Verification Engineer (4-15 Years)Mediatek is building Sub System DV teams in Bangalore to cater to the verification challenges in our next gen Smartphone, Compute and Automotive chips. We are seeking experienced Design Verification Engineers with 4-15 years of experience, specifically in subsystem verification or SoC verification, to join our highly...

Hi All,ACL Digital is hiring #Senior #Design #Verification Engineer!Experience: 4 Years Location: Bangalore / HyderabadNotice Period: Immediate to 30 Days Preferred!We're seeking experienced professionals ASIC/SoC verification. If you have expertise in UVM/System Verilog, proficiency in scripting languages like Python/Perl/TCL, and a strong grasp of...

Design Verification Engineer (5+ Years)Responsibilities:Develop, enhance, and maintain verification environments and testbenches using System Verilog and UVM.Create test plans from design specifications and contribute to coverage-driven and metric-driven verification goals.Build and integrate UVM components such as agents, monitors, scoreboards,...

About the RoleWe are seeking an experienced Design Verification Engineer to join our team and work on the verification of complex IP or subsystem blocks. The ideal candidate should have strong expertise in System Verilog, UVM methodology, and verification of high-performance interconnects and protocols.Key Responsibilities Execute IP or subsystem...

Design Verification Engineer - Senior / Lead / Sr. LeadJob Description:Must have good knowledge on the verification flows.Excellent hands-on debug skills and problem solving attitude..Experience of working in complex test-bench/model in Verilog, System Verilog or SystemCExperience of working on Functional Verification, SoC Verification, EmulationGood in...

Company DescriptionLeadIC Design Pvt Ltd is a semiconductor services company founded in 2018. LeadIC provides a range of services including IC Layout Design, Circuit Design, Digital Design and Verification, Physical Design and Verification, Characterization, and FPGA. The company has a presence in both India and Canada, catering to a global clientele.Role...

Role - Senior Design Verification EngineerExperience - 7+yearsLocation - Bangalore, Hyderabad, Pune and KochiNotice Period - Immediate to 60daysJD Design Verification• Understanding the business requirements and functional specifications of the IPs, subsystems and SOC• Creating Verification Environment Architecture document• Reviewing and Revising:...

12-14 yrs of work experiences in VLSI domain with Master's/bachelor's degree in engineering Strong expertise in Verilog, HVL(SV, Specman e) with UVM/OVM/eRM methodology Expertise in assertions development/closure, constraint randomization, functional and code coverages, formal verification Expertise in test-bench development Strong RTL and GLS (w/ or w/o...