Lead/Senior Design Verification Engineer

5 days ago

Bengaluru, Karnataka, India Excel Vlsi Technologies Full time ₹ 15,00,000 - ₹ 25,00,000 per year

Design Verification Engineer (5+ Years)

Responsibilities:

  • Develop, enhance, and maintain verification environments and testbenches using System Verilog and UVM.
  • Create test plans from design specifications and contribute to coverage-driven and metric-driven verification goals.
  • Build and integrate UVM components such as agents, monitors, scoreboards, sequencers.
  • Write, debug, and automate tests to verify complex RTL modules/IP blocks; perform test regression and analyse results.
  • Implement and analyse functional and code coverage metrics for quality signoff.
  • Work closely with design, software, and architecture teams for feature coverage and bug resolution.
  • Document verification results, coverage closure, and lessons learned; support tapeout and silicon bring-up as needed.

Requirements:

  • 5+ years experience with System Verilog and UVM-based digital verification.
  • Hands-on expertise in developing and debugging testbenches, test sequences, and UVM methodologies.
  • Solid understanding of RTL design principles and standard protocols (e.g., AMBA, PCIe, USB is a plus).
  • Experience with simulators (VCS, Questa, etc.), scripting (Perl, Python, Shell), and revision control tools (GIT/SVN).
  • Strong communication skills and ability to collaborate within cross-functional teams

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