
Memory Controller
1 day ago
Memory Controller - PrincipalLocation: HyderabadFounded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Bangalore A US based well-funded product-based startup looking for Highly talented Verification Engineers for the following roles. Memory Controller - Principal / Senior Staff Verification Engineers: looking for experienced and talented professional for DDR Memory Controller Verification.
Minimum Qualifications:BE/BTech in Electrical/Computer engineering with 10+ years of experience or ME/MTech in Electrical/Computer engineering with 8+ years of experience
Should have hands on experience in System Verilog, UVM/OVM and Object-Oriented ProgrammingProven track record in DDR5/LPDDR5X/LPDDR6/HBM4 IP verification from environment and tests development to validation closure
Work closely with RTL designers and SOC team to scope out integration and verification requirements
Proficiency in bus protocols AXI/AHBIntegration and verification of complex System IP features.Proficiency in scripting languages like Perl, Python etc.Strong communication, collaboration, and interpersonal skills
Strong analytical and problem-solving skills Preferred Qualifications:Experience in Memory controller, DDR4/5, LPDDR4/5, HBM memory protocols
Knowledge of Fabric/Network on chips, Cache CoherencyExperience in GLS is added advantage.Contact:UdayMulya ***************"Mining The Knowledge Community"
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Memory Controller
2 days ago
India Mulya Technologies Full time ₹ 15,00,000 - ₹ 20,00,000 per yearMemory Controller - Staff Verification EngineersLocation : HyderabadFounded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/Bangalore A US based well-funded product-based startup looking for Highly talented Verification Engineers for the following roles. Memory Controller - Staff...
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Staff Engineer
3 days ago
India Broadcom Full timeRole Lead and Execute Layout Design of SRAM CAM RF compiler memories in N3P N2P technology Responsibilities Development of key building blocks of memory architecture such as Row Decoder IO Control Skilled in pitched layout concepts floor planning for Placement Power and Global Routing Knowledge of EM IR requirements Compiler level integration ...
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