Lead Design Engineer

20 hours ago

Bengaluru, Karnataka, India L&T Technology Services Ltd. Full time ₹ 20,00,000 - ₹ 25,00,000 per year

Lead Design Engineer - Digital IP

LNT/LDE-DI/1471582

LTST-L&T Semiconductor Technologies LimitedBengaluru

Posted On

05 Sep 2025

End Date

04 Mar 2026

Required Experience

Years

Skills

Knowledge & Posting Location

RTL DESIGN

Minimum Qualification

BACHELOR OF ENGINEERING (BE)

Job Description

Position Overview:

In this role, you will be responsible for design and implementation of Digital IPs for cutting-edge SoC projects. Work on implementing IP definitions that meet customer and application needs. This role requires a strong background in design methodologies, hands-on experience with industry-standard tools, and the ability to lead/participate in design efforts from planning through execution.

Key Responsibilities:

Understand IP architecture, micro-architecture and register specification. Participate in specification writeup.

Participate in detailed performance, architectural and design requirement analysis with cross-functional teams, Vendors and customers.

Implement a specification using RTL coding techniques and best practices. Ensure complete Requirement spec implementation and traceability.

Collaborate with and provide guidance to the Post silicon and Software teams for prototype bring up and performance tuning.

Provide technical guidance to junior engineers and contribute to their professional development.

Qualifications/ Skills :

Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or a related field.

5 - 12 years of experience in designing and RTL coding using Verilog / System Verilog.

Exposure to verifying designs using module level testbench, UFM etc. Experience in using verification tools (VCS, Xcelium, Questa etc.), Lint/CDC/RDC tools (Spyglass, Questa CDC).

Experience in writing functional design doc and/or functional specifications.

Experience with low-power design techniques and power-aware design practices will be desirable.

Experience with Clocking, Reset, Mode Controller, Boot, Security IPs desirable.

Experience with Functional Safety standards for Automotive (ISO26262 etc), design care abouts, DFMEA analysis of IPs, is desirable.

Experience in usage of formal verification tools like Jasper-FPV, SEC while implementing designs will be a plus.

Good understanding of SoC architecture, including CPU, memory, Bus Protocols/ Interconnect and peripheral integration.

Good command over scripting and automation of tasks using Python, Perl, Tcl etc.

Good communication skills and the ability to work effectively within a team environment.

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