Lead Design Engineer
3 weeks ago
At Cadence we hire and develop leaders and innovators who want to make an impact on the world of technology Job Summary We are looking for a candidate with excellent communication skills and ability to ramp up on new technologies quickly and independently This position requires the technical expertise in DDR memory protocols such as DDR LPDDR GDDR preferably HBM4 This an excellent opportunity to work in a supportive and friendly work environment where we are vested in each others success and are passionate about technology and innovation Position Description Functional Verification Engineer role for DDR PHY Verification team Position is based in Bangalore The work involved will be working on building a new verification environment and testing various design features using the verification environment ensuring various customer configurations are clean as part of verification regressions supporting customers in case of any issues with using the verification environment and functional and code coverage As a part of delivery criteria the engineer would need to provide Demosim testbench with standard test patterns that aid as a reference for customer for seamless integration of our IPs The engineer would be responsible to ensure that the design is in line with the technical and quality requirements set for the team - particularly with respect to functional and code coverage Participate in technical discussions and represent verification team in all the discussions with internal and external customers Review all technical deliverables from team members and guide team members to meet quality and the schedule Fully accountable for quality design verification as per the schedule Track the verification progress identify potential risks and mitigation plan Mentor and provide technical guidance to team working in the projects Contribute to verification process and methodology improvements to boost efficiency and productivity Position Requirements Bachelors Masters degree in Electronics or Equivalent engineering stream 5 to 8 years of Design verification experience with a large portion of the recent work experience on verification environment development Strong background on functional verification fundamentals environment planning test plan generation environment development is a must Should have knowledge on all aspects of verification components verification metrics System Verilog experience and experience with UVM based functional verification environment development is mandatory Prior RTL Design experience using Verilog is a must - so that the verification engineer is self-sufficient for most aspects of debugging HBM4 Protocol experience is highly desirable Prior experience in functional verification and debugging of complex protocols is a must AXI3 4 experience is a desirable Prior experience in IP development teams would be an added advantage Behavioral skills required Must possess strong written verbal and presentation skills Good communication and interpersonal skills demonstrate teamwork and collaboration skills Ability to establish a close working relationship with both customer peers and management Explore whats possible to get the job done including creative use of unconventional solutions Work effectively across functions and geographies Push to raise the bar while always operating with integrity Were doing work that matters Help us solve what others cant
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Lead Design Engineer
3 days ago
Bengaluru, Karnataka, India Cadence Design Systems, Inc Full time ₹ 15,00,000 - ₹ 25,00,000 per yearAt Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer. • 4 years of Design Verification experience with SV/UVM • Strong background on functional verification fundamentals, environment...
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Data Entry Operator
7 days ago
Bengaluru, Karnataka, India Design Engineer Full time ₹ 2,64,000 per yearWe are seeking a dedicated and detail-oriented Data Entry Operator (DEO) to support R&D projects. The role involves accurate data entry, documentation, and maintenance of research records in secure systems. The DEO will assist scientists, engineers, and administrative staff by ensuring timely and error-free handling of project information.Key...
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Lead Design Engineer 07/09/2025
4 weeks ago
Bengaluru, Karnataka, India Cadence Design Systems Full timeAt Cadence we hire and develop leaders and innovators who want to make an impact on the world of technology Brief 1-3 sentences The Lead Analog Design Engineer will take a Key role on the Analog and Mixed signal design team as part of a Die to Die Product Development Team Job Responsibilities Design of High Speed D2D and SERDES products at industry...
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Verification Lead Design Engineer
3 weeks ago
Bengaluru, Karnataka, India Cadence System Design and Analysis Full timeBE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer.5+ years of Design Verification experience with SV/UVMStrong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.Design Verification experience verifying complex designs and...
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Verification Lead Design Engineer
3 weeks ago
Bengaluru, Karnataka, India Cadence System Design and Analysis Full timeBE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer.5+ years of Design Verification experience with SV/UVMStrong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.Design Verification experience verifying complex designs and...
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Physical Design Engineer
3 days ago
Bengaluru, Karnataka, India Eximietas Design Full time ₹ 20,00,000 - ₹ 25,00,000 per yearWe are seeking an exceptional Senior Physical Design Engineer to take a key role in our semiconductor design team. As a Senior Physical Design Engineer, you will lead the development and implementation of cutting-edge physical design methodologies and flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensure the...
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Lead Designer- Electrical
2 days ago
Bengaluru, Karnataka, India Space Matrix Design Consultants Full time ₹ 20,00,000 - ₹ 25,00,000 per yearSpace Matrix is a 23-year-old, Singapore-headquartered Design-led Build Organisation that has been redefining the world of workspaces. Over the years, Space matrix has evolved, expanding its expertise beyond interior design to encompass Data Centers and Life Science projects. Our commitment to excellence, innovation, and thought leadership has allowed us to...
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Design Verification Engineer
2 days ago
Bengaluru, Karnataka, India Eximietas Design Full time ₹ 20,00,000 - ₹ 25,00,000 per yearJob OverviewWe are seeking an experienced and highly skilled Senior SOC Design Verification Engineer with a minimum of 5 years of hands-on experience in SOC Design Verification. As a key member of our team, you will play a pivotal role in ensuring the robustness and correctness of our cutting-edge System on Chip designs.Job DescriptionLead and manage SOC...
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Senior Analog Layout Design Leads
4 weeks ago
Bengaluru, Karnataka, India Eximietas Design Full timeHiGreetings from Eximietas DesignWe are actively looking to hire Senior Analog Layout Design Engineers / Leads with (TSMC 5nm preferred) 7–15 years of experience to join our growing team. Locations: Bangalore. Notice Period: 30 days or less preferred.Job Description:We're seeking highly skilled professionals with a strong background in lower FINFET...
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Senior Analog Layout Design Leads
3 weeks ago
Bengaluru, Karnataka, India Eximietas Design Full timeHiGreetings from Eximietas DesignWe are actively looking to hire Senior Analog Layout Design Engineers / Leads with (TSMC 5nm preferred) 7–15 years of experience to join our growing team. Locations: Bangalore. Notice Period: 30 days or less preferred.Job Description:We're seeking highly skilled professionals with a strong background in lower FINFET...
