Display DV

General Summary:

Job Summary:

We are seeking a highly motivated and skilled Performance and Power Analysis Engineer to join our Display Systems team in Bengaluru. In this critical role, you will be responsible for the analysis, modeling, and optimization of performance and power consumption across various stages of our cutting-edge chip development process. You will take the lead and collaborate closely with architecture, design, Software and verification teams to ensure our products meet stringent performance targets and power efficiency requirements. As an independent collaborator, contribute with cross functional teams, SoC performance and SW/HW teams to enhance or optimize the process. This is an exciting opportunity to contribute to the development of next-generation semiconductor technology.

Responsibilities:

• Develop and maintain architectural-level and/or cycle-accurate models for performance and power estimation.
• Analyze trade-offs between performance, power, and area (PPA) at the architecture and microarchitecture levels.
• Drive performance and power analysis early in the design cycle to influence architecture and design decisions.
• Collaborate with architecture and design teams to explore and evaluate different design options and trade-offs to optimize performance and power.
• Conduct detailed analysis to identify performance bottlenecks and power inefficiencies in chip architectures and microarchitectures.
• Perform power profiling and characterization of designs under various operating conditions and workloads.
• Develop and implement power reduction techniques at different design stages (e.g., clock gating, power gating, voltage scaling).
• Analyze and debug performance and power-related issues during simulation, emulation, and silicon bring-up.
• Generate comprehensive reports and presentations summarizing analysis results and providing actionable recommendations to the design teams, cross-functional teams and senior leadership.
• Stay abreast of the latest industry trends, tools, and methodologies in performance and power analysis.
• Contribute to the development and improvement of internal tools and flows for performance and power analysis.
• Collaborate with verification teams to define and execute performance and power validation plans.
• Validate model accuracy through correlation with RTL simulations, emulation, and silicon measurements.

Minimum Qualifications:

Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience. ORMaster's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience. ORPhD in Engineering, Information Systems, Computer Science, or related field and 1+ year of Systems Engineering or related work experience.

Qualifications:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• 5 to 8+ years of experience in performance and power analysis for ASIC or SoC designs.
• Strong understanding of computer architecture, microarchitecture, and digital design principles.
• Strong experience in developing and utilizing performance and power models using languages such as SystemC, Python, C++, or custom in-house frameworks.
• Proficiency in using industry-standard performance and power analysis tools (e.g., Synopsys PrimeTime PX)
• Solid understanding of power management techniques and low-power design methodologies.
• Experience with simulation and emulation environments.
• Strong analytical and problem-solving skills with the ability to interpret complex data and draw meaningful conclusions.
• Excellent communication and interpersonal skills with the ability to collaborate effectively with cross-functional teams.
• Familiarity with silicon bring-up and post-silicon power/performance characterization is a plus.
• Experience with machine learning techniques for power/performance prediction is a plus.
• Experience with IOS and Xcode profiling/development is a plus