Senior Design Verification Engineer

2 days ago

Delhi, Delhi, India Talent Sniffers Full time ₹ 15,00,000 - ₹ 20,00,000 per year

Role Overview

We are seeking an experienced
Design Verification Engineer
with strong expertise in System Verilog/UVM and protocol-level verification. The candidate will be responsible for owning and driving the verification of blocks, subsystems, or SoCs, ensuring high-quality deliverables through extensive hands-on DV experience.

Key Responsibilities

  • Develop and execute
    test benches
    using System Verilog/UVM.
  • Own and drive the verification of a
    block, subsystem, or SoC
    .
  • Perform extensive
    IP/subsystem and SoC-level verification
    based on SV/UVM.
  • Conduct verification of industry-standard protocols such as:
  • PCI Express, UCIe, CXL, NVM
  • AXI, ACE, CHI
  • Ethernet, RoCE, RDMA
  • DDR, LPDDR, HBM
  • Work on
    ARM or RISC-V CPU-based subsystem or SoC verification
    using C/Assembly languages.
  • Perform
    Power Aware Simulations
    using UPF.

Must-Have Skills

  • Strong expertise in
    System Verilog/UVM
    .
  • Proven experience in
    Test Bench development
    .
  • 8+ years of
    hands-on DV experience
    .
  • Deep understanding of
    IP, subsystem, and SoC verification
    methodologies.
  • Experience with
    protocol verification
    across one or more of the following domains: PCIe/UCIe/CXL/NVM, AXI/ACE/CHI, Ethernet/RDMA, DDR/LPDDR/HBM.
  • Familiarity with
    CPU subsystem verification
    (ARM/RISC-V).
  • Proficiency in
    Power Aware Simulations (UPF)
    .

Location: Bangalore, Hyderabad, Pune, Kochi - Hybrid Mode

Client: Wipro

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