Senior Design Verification Engineer

2 weeks ago

Bengaluru, Karnataka, India ACL Digital Full time ₹ 15,00,000 - ₹ 20,00,000 per year

Lead/Senior PCIe IP Verification Engineer Experience : 5+ yearsLead/Senior PCIe IP Verification Engineer with strong expertise in PCIe Endpoint IP verification, either as a standalone block or integrated within a subsystem. The ideal candidate will have at least 5 years of experience in PCIe RTL design verification with a deep understanding of PCIe protocol (Gen3/Gen4/Gen5 or beyond) and modern verification methodologies. Key Responsibilities:Own and drive functional verification of PCIe Endpoint IP at block and subsystem levels.

Develop and maintain SystemVerilog/UVM-based testbenches and reusable verification components (UVCs). Define and execute detailed verification plans based on functional specifications and architecture documents. Write and debug testcases, assertions, and checkers to validate PCIe Endpoint behavior, including link training, flow control, power management, and error handling.

Drive functional coverage closure and regression stability for IP releases. Collaborate closely with RTL design, architecture, and firmware/software teams. Support debug and triage of issues discovered during pre-silicon simulation and post-silicon validation.

Continuously improve verification infrastructure, including scripting, automation, and methodology. Required Qualifications:Bachelor's or Master's degree in Electrical/Computer Engineering or related discipline.5+ years of hands-on experience in IP-level RTL verification. Deep understanding and verification experience of the PCIe Endpoint protocol (Gen3/Gen4/Gen5 or Gen6).

Strong command of SystemVerilog, UVM, and industry-standard simulators and debug tools (VCS, Questa, Verdi, etc.). Experience writing coverage models, constraints, and assertion-based verification (SVA). Strong debugging and analytical skills with the ability to root-cause issues in both RTL and testbench environments.

Excellent communication and documentation skills. Preferred Qualifications:Experience with PCIe IP bring-up, compliance testing, and formal verification. Familiarity with subsystem integration, including AXI/APB interfaces and other AMBA protocols.

Hands-on experience with low-power verification, clock-domain crossing (CDC), and reset-domain crossing (RDC) checks. Proficiency in scripting languages (Python, Perl, Shell, TCL) for regression and automation tasks. Experience working with VIPs (e.g., Cadence, Synopsys PCIe VIP).

Interested please share your updated resume to *************

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