Senior Design Verification Engineer

4 weeks ago


Bengaluru, Karnataka, India Tessolve Full time

Job Title: Senior Design Verification Engineer – IP/SoC/Processor/GLS

Experience: 5 to 15 Years

Location: (Insert Location – e.g., Bangalore / Hyderabad / Chennai / Noida )

Company: Tessolve Semiconductor

Job Type: Full-Time | Permanent

Domain: Semiconductor – Design Verification

Job Summary:

Tessolve is hiring experienced Design Verification Engineers with a strong background in IP and SoC-level verification , along with specialization in one or more of the following areas: processor/microarchitecture verification , high-speed interfaces (e.g., PCIe, USB, DDR) , or GLS (Gate-Level Simulation) . This role involves ownership of verification strategy, planning, and execution in pre-silicon environments using industry-leading tools and methodologies.

Key Responsibilities:

  • Develop and execute detailed verification plans for IP blocks, subsystems, or SoCs.
  • Design and build SystemVerilog/UVM-based testbenches , scoreboards, monitors, and drivers.
  • Subject Line: Senior DV Engineer – IP/SoC/Processor/GLS – (Your Name)

    • Learn more:


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