Lead Engineer

2 weeks ago

Bengaluru, Karnataka, India Fiveforce Techno Solutions Full time ₹ 12,00,000 - ₹ 24,00,000 per year
Position: Lead Engineer – DFT (Design for Testability)
Location: Bangalore
Experience: 8–12 years
Employment Type: Full-time
 
We are seeking a highly skilled Lead DFT Engineer to drive the design-for-test architecture, implementation, and verification for complex SoCs and ASICs. The ideal candidate will have strong expertise in industry-standard DFT methodologies and hands-on experience in architecting, developing, and delivering high-quality test solutions for high-volume production silicon.

DFT Architecture & Implementation

  • Define and develop DFT architecture for SoCs/ASICs including scan insertion, compression, ATPG, MBIST, LBIST, and boundary scan.

  • Lead full-chip DFT integration, including RTL-level DFT insertion and test-mode logic.

  • Own testability requirements, design rules, and coverage targets.

ATPG & Coverage

  • Plan and execute ATPG for stuck-at, transition, path delay, bridging, and other fault models.

  • Analyze test coverage and drive improvements through design and pattern optimizations.

  • Develop test programs for ATE platforms (e.g., Advantest, Teradyne).

DFT Verification

  • Create and execute DFT verification plans (DFT sims, JTAG verification, MBIST/BIST validation).

  • Debug and resolve DFT-related issues at block and full-chip level.

Silicon Bring-up & Production Support

  • Support silicon bring-up, test program debugging, and characterization.

  • Collaborate with product engineering and test teams for production ramp-up.

  • Drive yield improvement and test time reduction strategies.

Collaboration

  • Work closely with RTL designers, physical design teams, and test engineers.

  • Provide mentorship to junior DFT engineers and contribute to best practices.

Required Skills & Experience

  • Bachelor's/Master's degree in Electronics, Electrical, VLSI, or related field.

  • 8+ years of hands-on experience in DFT for complex SoCs/ASICs.

  • Strong expertise in:

    • Scan insertion and compression (Mentor Tessent / Synopsys DFTMAX / Cadence Modus).

    • ATPG pattern generation and coverage analysis.

    • MBIST/LBIST architecture and implementation.

    • JTAG / IEEE 1149.x boundary scan standards.

  • Experience with simulation tools: VCS, Questa, etc.

  • Understanding of SoC architecture, RTL design, timing closure, and floorplanning.

  • Experience supporting ATE bring-up (Teradyne, Advantest).

  • Strong debugging, analytical, and problem-solving skills.

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