Senior ASIC
1 week ago
We are looking for skilled Senior ASIC/SoC RTL Engineer / Lead / Managers with 5-20 years of experience to join our team in Bangalore, Chennai, Hyderabad, Kochi, Pune, Noida, and Ahmedabad. The ideal candidate will have expertise in SoC/IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog, AMBA bus protocols (AXI, AHB, ATB, APB), interface protocols, and scripting languages like Make flow, Perl, shell, and Python.
Roles and Responsibility
- Design and develop high-quality ASIC/SoC RTL code.
- Lead the development team in integrating subsystems and clusters at the SoC level.
- Collaborate with cross-functional teams to ensure successful project execution.
- Develop and maintain technical documentation for designs and implementations.
- Troubleshoot and debug complex issues related to ASIC/SoC design and integration.
- Mentor junior engineers to improve their skills and knowledge.
Job Requirements
- Technical graduation with exact domain experience in RTL design.
- Expertise in SoC/IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog.
- Proficiency in AMBA bus protocols (AXI, AHB, ATB, APB) and interface protocols.
- Experience with scripting languages like Make flow, Perl, shell, and Python.
- Strong understanding of digital design principles and methodologies.
- Excellent problem-solving skills and attention to detail.
- Notice period: 0-45 days.
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