DV CPU Verification Coherency
5 hours ago
Position Overview
We are seeking a highly skilled and experienced Design Verification (DV) Engineer to join our core silicon engineering team. You will be at the forefront of verifying our next-generation, high-performance, and power-efficient CPU complexes and SoCs. This role demands a deep expertise in CPU architecture, coupled with specialized knowledge in low-power design, complex clocking schemes, and high-speed protocols.
You will be responsible for ensuring the functional correctness of the most critical components of our chips, tackling complex challenges that directly impact product performance and quality.
Key Responsibilities- Develop and execute comprehensive, feature-driven verification plans for multi-core CPU subsystems, cache hierarchies, and memory management units.
- Architect, implement, and maintain robust, scalable, and reusable verification environments using SystemVerilog and UVM.
- Take ownership of verifying low-power design features, including power-gating, dynamic voltage and frequency scaling (DVFS), and retention, using UPF-based power-aware simulation methodologies.
- Lead the verification effort for designs with multiple asynchronous clocks, employing advanced Clock Domain Crossing (CDC) analysis and verification techniques.
- Verify the integration and functionality of high-speed peripheral protocols such as UFS, PCIe, and USB.
- Debug complex hardware bugs at the IP and SoC level, and drive them to resolution by working closely with architecture and design teams.
- Develop comprehensive functional coverage models and actively work towards achieving coverage closure to ensure thorough verification.
- Contribute to improving verification methodologies and automation to enhance team productivity.
- Bachelor's or Master's degree in Electrical/Computer Engineering or a related field.
- 5+ years of hands-on experience in ASIC/SoC Design Verification.
- Direct and substantial experience in CPU verification, including a strong understanding of processor architecture (pipelines, instruction sets, caches, MMU).
- Expert-level proficiency in SystemVerilog and the Universal Verification Methodology (UVM).
- Proven ability to debug complex system-level failures and identify root causes.
- Low Power Verification: Deep, practical experience with the Unified Power Format (UPF) and verifying complex low-power management schemes.
- Clock Domain Crossing (CDC): Proven experience with CDC verification tools (e.g., SpyGlass, Questa CDC) and methodologies for ensuring correctness in multi-clock designs.
- High-Speed Protocols: In-depth knowledge and verification experience with at least one of the following: UFS, PCIe, or USB.
- Cache Coherency: Experience verifying cache coherency protocols (e.g., MESI, MOESI) in multi-core CPU environments is a significant plus.
- Scripting & Automation: Strong scripting skills in languages like Python, Perl, or Tcl for automation of verification flows.
- Formal Verification: Familiarity with formal verification techniques and tools is highly desirable.
- Gate-Level Simulation (GLS): Experience with running and debugging gate-level simulations with SDF back-annotation.
- Soft Skills: Excellent communication skills and the ability to work effectively in a collaborative team environment.
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