Verification Engineer – Digital
2 days ago
Job Title: Verification Engineer – Digital
Location: Bangalore (Work From Office)
Employment Type: Full-time
Experience Required: 5–13 years
We are seeking a skilled and detail-oriented Digital Verification Engineer with a strong background in mixed-signal devices and expertise in SystemVerilog and UVM methodologies. The ideal candidate will have hands-on experience in developing verification environments and driving block-level to chip-level verification efforts in a fast-paced engineering environment.
Key ResponsibilitiesDevelop verification environments and testbenches for block, subsystem, and chip-level verification using SystemVerilog/UVM.
Collaborate closely with design teams to integrate design changes into verification flows.
Perform simulations and debug using gate-level netlists across multiple PVT corners.
Handle VCD generation for power analysis and contribute to DFT validation and ATPG simulations.
Apply code and functional coverage metrics to drive verification completeness.
Write and maintain scripts using Perl, Python, or Shell to support automated verification workflows.
Coordinate with analog and architecture teams for mixed-signal integration and model handling.
Support bring-up and characterization lab activities, including FPGA-based validation platforms.
Provide support in resolving customer debug queries and delivering timely technical solutions.
Bachelor's or Master's degree in Electrical, Electronics, or a related technical discipline.
5–13 years of hands-on experience in digital verification.
Strong expertise in SystemVerilog, UVM, and scripting languages.
Solid understanding of digital fundamentals, DFT concepts, and mixed-signal integration.
Proven debugging and problem-solving skills.
Excellent team collaboration and communication abilities.
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