Senior Technical Architect

6 days ago

Bengaluru, Karnataka, India Quest Global Full time ₹ 20,00,000 - ₹ 25,00,000 per year

Job Requirements

Role Summary:

This is a deep technical leadership role focused on architecting and guiding turnkey SoC physical design projects. The ideal candidate will have extensive hands-on expertise in RTL2GDS implementation at advanced nodes (3nm/5nm), be customer-facing, and capable of owning project methodology, technical quality, and solution engineering end to end.


Key Responsibilities:

Turnkey Delivery Leadership

  • Define and drive end-to-end RTL-to-GDSII flows, tailored for customer-specific technology, tools, and deliverables.
  • Lead complex top-level and hierarchical SoC designs, ensuring quality and signoff compliance.
  • Guide floorplan strategy, power planning, PPA closure, IR/EM signoff, and integration challenges.

Customer Engagement

  • Understand customer requirements and provide technical solutions, execution strategies, and staffing recommendations.
  • Interface with customer architects and stakeholders for reviews, issue resolution, and milestones.

Technical Mentorship

  • Mentor physical design teams on advanced technology node implementation, complex SoC partitioning, and tool optimizations.
  • Review block-level signoff issues, methodology gaps, and drive technical excellence across projects.

Flow Development and Innovation

  • Own and refine PD reference flows, checklists, automation scripts, and ECO methodologies.
  • Drive low power implementation (UPF), hierarchical signoff closure, and flow correlation across synthesis, STA, and physical domains.

Work Experience

Skills & Experience Required:

  • 1522 years of hands-on experience in physical design implementation. Lead multiple complex design Tapeouts on advance tech nodes.
  • Deep Expertise in PD tools and flows covering synthesis, STA, PNR, Signoff domain. Eg. Synopsys Fusion Compiler, ICC2, PrimeTime, ICV, Cadence Innovus/Tempus, Ansys RedHawk, Caliber, UPF, CLP etc..
  • Strong grasp of low power flows, multi-voltage/multi-Vt, UPF, and power intent checks.
  • Experience in managing or technically driving multiple successful tapeouts (including full-chip or subsystems).
  • Strong scripting in TCL, Python, and ability to drive flow optimizations.
  • Excellent problem-solving, debugging, and documentation skills.
  • Prior customer-facing or solution architect experience preferred.

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