Low Power SoC Verification
1 day ago
Position Name - Low Power SoC Verification Experienced in ASIC/SoC verification with 4+ years focusing on low-power design. Proficient in SV UVM, power-aware simulation, and tools like Synopsys, Cadence, and Mentor for power analysis. Skilled in low-power design techniques (e.g., clock gating, power gating, DVFS) and UPF/CPF-based verification. Familiar with scripting languages (Python, Perl, TCL) for automation and power optimization techniques. Knowledgeable in functional safety standards like ISO 26262 for automotive applications.
Experience:
- 4+ years of experience in ASIC/SoC verification, with a focus on low-power design verification.
- Solid Experience on SV UVM
- Hands-on experience with power-aware simulation and verification tools.
- Familiarity with low-power design techniques, such as clock gating, power gating, and dynamic voltage/frequency scaling (DVFS).
- Proficiency in low-power UPF/CPF-based verification
- Familiarity with EDA tools for power analysis and verification (e.g., Synopsys, Cadence, Mentor).
- Experience with scripting languages like Python, Perl, or TCL for automation.
- Knowledge of power estimation and optimization techniques.
- Familiarity with functional safety standards (e.g., ISO 26262 for automotive applications)
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