Senior SOC Design Verification Engineer
3 days ago
Role & responsibilities
- Be part of a team to verify complex system on a chip designs. Interact with design engineers to identify important verification scenarios.
- Create and enhance constrained-random verification environments using UVM/ SystemVerilog
- Create complex C/SV tests using reusable test libs.
- Team player and a mentor who is self-driven, motivated and guides a team of junior engineers
- Responsible for quality and timeliness of the team output
Preferred candidate profile
- Bachelor's/ master's degree in electrical engineering or computer science, with 5-10 years of relevant experience.
- Experience with digital system based on AMBA Bus protocols like ACE/AXI/AHB/APB or similar complexity bus protocols.
- Experience with System Verilog Assertions with industry standard tools a plus
- Experience with SOC boot flow, clocking and platform bring up in Emulators or Silicon desired
- Experience with Low Power Verification and power management flows.
- Experience with RTL, GLS level simulations
- Knowledge and Experience working on PCIE/Ethernet and other HSIO desired
- Experience in UVM/OVM based Methodology Development.
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