Principal Member Technical Staff

2 weeks ago

India Smart Soc Solutions Full time

Job Description

  • Solid Experience in DFT Architecture.

  • The candidate should have experience with ATPG, JTAG, BSCAN, BIST and MBIST flows.

  • Experience on Hierarchical DFT techniques using Pattern Retargeting in Tessent flow

  • Strong knowledge of the Tessent Shell environment and Tessent tools

  • The desired candidate must have specific emphasis on the following tools Test Kompress / Fastscan ATPG, MBIST, Boundary scan.

  • Hands on experience in simulating scan patterns and debugging pattern mismatches during verification process

  • Experience in helping to debug failing scan patterns on the ATE is highly desirable.

  • Hands on knowledge in state-of-the-art EDA tools for DFT, design and verification.(Mentor, Cadence, Synopsys)

  • Must be able to simulate and debug MBIST testbenches.

  • Ability to come up with a detailed test plan based on the Arch specs

  • Should be knowledgeable in all SOC functions such as Digital design, STA, Synthesis, PnR, DV and ATE test.

  • The candidate should have prior experience in managing and developing teams

Required Qualification : B.E / B.Tech / M.E / M.Tech in Electrical / Electronic Engineering.

experience-10-16 years

  • Preferred experience of handling 10+ team members.

  • Good understanding and exposure to SoC design and architecture

  • Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects

  • Comfortable with VCS / Verdi and excellent debugging skills


• Logical in thinking and ability to gel well within a team and be a proactive member of the team.
• Good communication and leadership skills

  • Excellent team player

  • High Integrity

Job Type: Full Time

Job Location: Hubballi

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