Analog Design Engineer
2 days ago
Role: Analog Layout Design Engineer
Client: Samsung
Location: Bangalore
Exp: 5+ Years
Work Basis: Fulltime
Job Description: Analog Layout Engineer (5+ Years Experience)
Position Overview:
We are seeking an experienced Analog Layout Engineer with 5+ years of hands-on expertise in deep sub-micron CMOS layout design. The ideal candidate will be responsible for custom layout implementation of analog, mixed-signal, and RF blocks, ensuring compliance with design rules, matching requirements, and performance specifications.
Key Responsibilities:
Perform full-custom analog and mixed-signal layout design including op-amps, comparators, ADC/DAC blocks, PLLs, LDOs, bandgaps, high-speed I/Os, and memory-related circuits.
Ensure device matching, symmetry, shielding, and routing practices to meet stringent analog performance requirements.
Collaborate closely with circuit design engineers to understand schematic intent, performance trade-offs, and physical design constraints.
Conduct DRC, LVS, ERC, and parasitic extraction (PEX) verification to ensure design integrity and functionality.
Work on floorplanning and block-level integration for complex analog/mixed-signal SoCs.
Optimize layouts for area, performance, and reliability, considering IR drop, electromigration, and ESD guidelines.
Provide support during tape-out, silicon validation, and debug phases.
Mentor junior layout engineers and review layout quality for adherence to best practices.
Required Skills & Qualifications:
B.E/B.Tech/M.Tech in Electronics, VLSI, or related discipline.
5+ years of experience in custom analog/mixed-signal layout design in advanced CMOS technology nodes (e.g., 28nm, 16nm, 7nm, or below).
Proficiency with EDA tools such as Cadence Virtuoso, Mentor Calibre, Synopsys IC Validator, etc.
Strong understanding of analog layout techniques: device matching, common-centroid, interdigitated layout, shielding, guard rings, and latch-up prevention.
Experience with parasitic-aware layout and post-layout simulation flows.
Familiarity with ESD protection layout, reliability checks, and power-ground planning.
Good communication skills and ability to work in a team-oriented environment.
Preferred (Nice-to-Have):
Experience in RF layout (LNAs, VCOs, mixers, PA) or high-speed SerDes/DDR/PCIe interfaces.
Knowledge of FinFET technologies and multi-patterning constraints.
Exposure to automated layout generation tools or scripting (SKILL, Python, Tcl).
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