Staff FPGA/Soc Integration Engineer

Job Description

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B) global organization? We offer all that and more at Microchip Technology Inc.

People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchips nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and its won us countless awards for diversity and workplace excellence.

Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.

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The staff FPGA/SoC integration engineer will be responsible for integrating all custom and external IPs into the FPGA top. This high visibility role involves ownership of chip top RTL, place/route and timing closure and other deliverables needed to release the FPGA for production.

Duties & Responsibilities

• Develop flows and methodologies that improve on current methodology to integrate complex IPs into FPGA chip-top using digital-on-top (DoT) approach.
• Develop tools and scripts (RTL and custom scripts) to verify connectivity and functionality of chip-top.
• Own chip level floorplan activities, place and route, timing closure, and physical and electrical verification.
• Coordinate activities between different groups like architecture, design, software, and verification to ensure smooth integration of various IPs into the chip top.
• Generate netlists with different views for software, physical, electrical, and functional verification.
• Collaborate with the packaging team to generate package files for several different members of the FPGA product family.
• Work with the verification team to help debug chip top-level integration issues related to timing and functionality.
• Effectively present technical information to small teams of engineers.
• Communicate regularly with the management, design, and verification teams in multiple locations to resolve issues, update status, and solve technical problems related to chip/SoC integration and delivery.
• Become well-versed in new ASIC and custom tools related to chip integration.

Requirements/Qualifications: Experience Required

• Minimum of 15 years of proven silicon design experience in ASIC design flow including RTL design, implementation, functional validation.
• Extensive knowledge of integration of several complex custom and ASIC IPs at chip-top level using DoT (digital on top) methodology.
• Expert in ASIC flow and methodology.
• Experience with System Verilog/Verilog, synthesis, STA, and place and route is required.
• Expert in the usage of ASIC tools like Innovus, Tempus, Magillem, Verdi or similar is required.

Other Requirements

• Demonstrated competency in scripting, managing simulation queues, and data capture plus presentation using Microsoft Office tools, including Excel.
• Ability to support layout, verification, timing characterization, and software model developers.
• Good analytical, oral, and written communication skills.
• Able to write clean, readable presentations.
• Self-motivated, proactive team player.
• Ability to work to schedule requirements.

Beneficial Experience

• Experience in ASIC development, several technology nodes.
• Experience with verification methodologies such as SystemVerilog/UVM.
• Experience in low power design.

Qualification:

• Bachelor's or Masters in Electrical Engineering, Physics, Computer Engineering, or Computer Science preferred.

Travel Time:

• No Travel

To all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.

Locations - India - Hyderabad

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