GLS Verification

4 days ago


Bengaluru, Karnataka, India Tessolve Full time ₹ 20,00,000 - ₹ 25,00,000 per year

Key Responsibilities:

  • Perform gate-level simulations (GLS) for ASIC/SOC designs post-synthesis and post-layout.
  • Validate timing, power-up behavior, clock gating, and low-power modes (with UPF/CPF).
  • Develop and execute GLS test plans including functional, scan, and ATPG pattern verification.
  • Work closely with RTL design, DFT, STA, and backend teams for issue resolution.
  • Debug timing-related issues in post-layout netlist simulations.
  • Ensure zero-delay and SDF-annotated simulation coverage.

Requirements:

  • Strong experience in GLS verification at the netlist level with SDF annotation.
  • Solid understanding of timing closure, STA concepts, and simulation tools.
  • Proficient in SystemVerilog, scripting (Perl, Python, or Tcl), and waveform debugging.
  • Familiarity with tools like VCS, Questa, Xrun, PrimeTime, Verdi.
  • Experience with low-power verification using UPF/CPF is a strong plus.
  • Strong debugging, documentation, and team collaboration skills.

Preferred Profile:

  • 512 years of relevant industry experience.
  • Previous experience in GLS closure for complex SoCs.
  • Exposure to DFT/Scan/ATPG verification is desirable.
  • Immediate availability or 15 days notice period.Role & responsibilities

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