Lead Design
5 days ago
Hiring: Design Verification Engineers
Bengaluru / Noida / Pune / Remote
7–15 years' experience
Skills: UVM, System Verilog, Functional Verification, Testbench Development, Debugging
Roles & Requirements:
DV Engineer – MAC Protocol
Experience: 4+ years overall
Must-have: Minimum 2 year of hands-on MAC protocol experience
DV Engineer
Experience: 4+ Years
Skills Required:
System Verilog, UVM, Testbench Development
Functional Coverage, Assertions, Debugging
Protocols – AMBA, PCIe, USB, DDR, Ethernet
IP / SoC Level Verification
Availability: Immediate joiners or within 30 days preferred.
Kindly share your update resume with the Client name and the duration of the projects to ,You can reach out to me
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