Lead DFT Engineer

Job Title : DFT EngineerJob Description :Responsibilities :- Develop and implement DFT architectures including scan insertion, ATPG, memory BIST, and boundary scan.- Generate and validate ATPG patterns for stuck-at, transition delay, and other fault models.- Perform memory BIST insertion, simulation, and verification.- Work with physical design team to...

Overview:WHAT YOU DO AT AMD CHANGES EVERYTHINGWe care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded....

We are hiring DFT Engineer | HyderabadNotice Period: 30 DaysPosition: DFT EngineerLooking for passionate professionals with 4 to 6 years of experience in Design for Test (DFT) to join our growing team in HyderabadKey Responsibilities:Drive innovative DFT implementation at RTL and Gate level for SoC designs at both hard macro and chip top level, including: ...

Role : DFT Integration Engineer Experience : 4 to 7 years Location : Hyderabad Preferable : Immediate to 30 days notice Requirement: Experience to work on DFT RTL side of things including RTL edt/SSN/MBIST insertion. Should have good hold on streaming through RTL files, debugging from log pointers. Good understanding of DFT architecture is desired. SSN, TAP...

Role : DFT Integration EngineerExperience : 4 to 7 yearsLocation : HyderabadPreferable : Immediate to 30 days noticeRequirement:Experience to work on DFT RTL side of things including RTL edt/SSN/MBIST insertion.Should have good hold on streaming through RTL files, debugging from log pointers.Good understanding of DFT architecture is desired.SSN, TAP...

Hello Connections,Greetings from ElevarSoCWe are hiring forSenior DFT Engineerwith5+ YearsofExperienceforHyderabad location.hashtag#Hyderabad /Immediate / 2 weeks preferredhashtag#Below the jdTechnical Skill:·       Performing  Automotive SoC – ASIL D project DFT activities at block and Full chip level.·       DFT schemes: LBIST, PMBIST,...

Experience: 10+ yearsShould have worked hands-on extensively on full chip DFT design,implementation, vector generation/verification, JTAG, boundary scan and simulation.-Experience with Scan, Compression, ATPG and simulations with Mentor/Synopsys/Cadence tools. Logic BIST knowledge is a plus. - Should have participated in successful tapeouts ofSoC/ASIC chips...

Should have worked hands-on ASIC DFT design,implementation, vector generation/verification, JTAG, boundary scan and simulation.-Experience with Scan, Compression, ATPG and simulations with Mentor/Synopsys/Cadence tools. Logic BIST knowledge is a plus. - Should have participated in successful tapeouts ofSoC/ASIC chips at Lower nodes ; 14nm or below and...

Job DescriptionWe are looking for an adaptive, self-motivative DFT engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMDs abilities to deliver the highest quality, industry-leading technologies to market. The DFT team furthers and encourages continuous technical innovation to showcase successes...

Role & responsibilitiesHandling hierarchical scan insertion ATPG flow.Integration and Verification of MBIST at RTL level.RTL Integration, Verification, gate level Coverage and GLS enablement for LBIST.Implementation and Verification of IEEE1149.1 JTAG, IJTAG standards.Post silicon debug activities for DFT patterns.Collaboration with RTL design, Physical...