Senior/Lead Static Timing Analysis Engineer

4 days ago


Hyderabad, Telangana, India Synopsys Inc Full time ₹ 20,00,000 - ₹ 25,00,000 per year

We are seeking an experienced, highly motivated and high-caliber individual to build these differentiating products. Does this sound like a good role for you?

  • Senior/Lead STA Engineer (R&D Engineering)
  • Location:
    Hyderabad & Bhubaneswar & Bangalore
  • Experience:
    5yrs to 15yrs
  • Strong experience in STA concepts
    , tools and methodologies at IP/subsystem/chip levels
  • Hands-on experience in
    Synthesis, pre-layout STA, post-layout STA, CTS tools
  • Ability to understand IP/subsystem design and come up with STA plan/checkers and reviews
  • Sound knowledge of standard ASIC RTL2GDS physical implementation and signoff flows
  • Exposure to design implementation and signoff of soft & mixed-signal IPs and subsystems
  • Experience in Functional, DFT (scan-shift, scan-capture and at-speed) mode constraints development and timing closure with MCMM (multi-corner, multi-mode)
  • Proficiency with Backend & STA tools from any EDA vendor, preferably Synopsys tools like PrimeTime, ICC2, Design Compiler, Fusion Compiler (or equivalent) used in the RTL2GDSII implementation
  • Good understanding of OCV, POCV, derates, crosstalk and design margins
  • Experience with design methodologies like developing custom scripts and enhancing flows for better execution. Experience in scripting with TCL/PERL is required
  • Exposure to design implementation and signoff of soft & mixed-signal IPs and subsystems

Please share your updated CV with

or refer those who would like to explore this opportunity.

  • Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, gender identity, age, military veteran status, or disability.

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