
Design Verification Manager
1 week ago
DV Manager: 12+ Years
Location: Bangalore
Notice: Days
SummarySenior technical leadership position responsible for ASIC/RTL design verification, team management, and implementation of verification strategies using advanced tools and methodologies.
Key ResponsibilitiesResponsibilities
1Lead and manage verification team of 10+ members (Must have)
2Develop and implement verification strategies using System Verilog
3Oversee OVM/UVM implementation and verification processes
4Manage simulation environments across multiple platforms (Synopsys/Mentor Graphics/Cadence)
5Drive scripting and automation initiatives
6Lead debugging and analysis of complex digital design issues
7Oversee verification of processor subsystems
8Manage validation suite creation and automation
9Guide silicon bring up and testing processes
10Ensure quality and completeness of verification deliverables
Qualifications & SkillsEducationB.E/B.Tech/M.E/M.Tech in Electrical/Electronic Engineering
Experience12+ years in ASIC/RTL design verification
Skills: System Verilog Testbench Architecture, OVM, UVM expertise, Simulator tools (Synopsys/Mentor Graphics/Cadence), Scripting languages (Perl, Python, Shell, Tcl/Tk), Hardware verification languages (SystemVerilog, SystemC), Hardware description languages (Verilog, VHDL), AMBA, AHB, AXI, JTAG protocols, Gate-Level Simulation and Debugging, Processor subsystems (ARM/RISC), Silicon testing and bench application.
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