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Manager - Design Verification
2 weeks ago
Job description Position: Engineering Manager – Design Verification Location: Bangalore Experience: 12 years Domain: ASIC/SoC Design Verification About KeenSemiKeenSemi is shaping the future of India's semiconductor design landscape by delivering high-impact design services with precision and ambition. From RTL design to GDSII, our capabilities span across key domains including Functional Verification, DFT, Physical Design, and Custom Layout. We support some of the world's most advanced semiconductor companies, helping them build high-performance chips from the ground up.
We are engineers, problem-solvers, and collaborators — committed to building a culture where innovation meets execution. If you're driven to lead teams, scale technology, and contribute to the growth of a next-gen semiconductor company, KeenSemi is your platform. Why
Work With Us?
Step into a leadership role at one of India's most promising semiconductor design services firms. Influence both technical execution and strategic direction in verification services. Join a forward-thinking team that values ownership, clarity, and long-term impact.
Collaborate directly with leading global semiconductor companies and be part of shaping cutting-edge silicon products. Role OverviewWe're on the lookout for a seasoned verification leader who can take charge of our ASIC/SoC verification programs. As Engineering Manager, you'll not only own project delivery and quality but also scale a top-tier verification team, define future-ready methodologies, and partner closely with customers and cross-functional leaders.
What You'll Be Responsible ForSpearhead the complete verification lifecycle — from planning strategies to achieving final sign-off for silicon readiness.
Design and implement scalable, modular, and reusable testbenches and workflows for both IP and SoC levels. Lead verification across a range of complex interfaces — from PCIe and CXL to DDR, HBM, and peripheral protocols like SPI, I2C/I3C, UART, GPIO, and MIPI.Ensure robust low-power validation using methodologies like UPF and X-prop. Set high standards for sign-off, including functional, code, and toggle coverage, and assertion-based verification.
Collaborate with design, firmware, DFT, and post-silicon teams to ensure system-level validation and issue resolution. Build and nurture a high-performance team of verification engineers, driving both technical depth and process discipline. Manage integration of third-party Verification IPs (VIPs) and build strong relationships with EDA vendors.
Enable SoC-level testing using embedded software alongside SystemVerilog environments. Continuously refine tool flows and infrastructure, leveraging scripting and automation for better efficiency. What
We're Looking ForAt least 12 years of deep experience in ASIC/SoC verification, with a strong track record of technical leadership. Hands-on expertise in SystemVerilog, UVM, and advanced coverage-driven verification methodologies. Experience delivering complex SoCs from specification to production, including successful first-silicon results.
Solid grounding in power-aware and low-power verification strategies (UPF, simulation with power intent). Proficiency in debugging complex issues and automating workflows using Python, Shell, Perl, or similar. Exceptional leadership, mentoring, and communication skills — with a proven ability to manage and scale engineering teams across geographies.
