
Design Verification Engineer
6 hours ago
Job Title: Design Verification Engineer (3+ Years)
Location: Bangalore
Experience: 3+ Years
Joiners: Immediate
Job Description:
We are looking for an experienced Design Verification Engineer with hands-on expertise in SystemVerilog (SV) and UVM-based verification projects. The ideal candidate should have strong problem-solving skills, exposure to block/IP level verification, and the ability to work independently in a fast-paced environment.
Key Skills:
3+ years of experience in Design Verification
Strong knowledge of SystemVerilog & UVM methodology
Experience in testbench development, debugging, and regression management
Good understanding of RTL, simulation, and verification flow
Excellent communication and teamwork skills
Eligibility:
Immediate joiners preferred
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