EM and IR Drop Analysis

WHAT YOU DO AT AMD CHANGES EVERYTHINGAt AMD, our mission is to build great products that accelerate next-generation computing experiences – from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create...

WHAT YOU DO AT AMD CHANGES EVERYTHINGAt AMD, our mission is to build great products that accelerate next-generation computing experiences – from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create...

Understanding of power delivery networks (PDN) and power integrity conceptsAnalysing and  IR drop, across the power grid on multi Power domain / Voltage AreaEM Analysis and current density checkPower rail / PDN analysis, rail current and checksDeveloping and implementing techniques to reduce power consumption, such as power gating and voltage islandsPerl,...

Looking for EMIR EngineerJob location- Bangalore.Exp.-4+yrsPrefer- Immediate joiner or less notice period.Key Responsibilities:Perform IR drop and Electromigration (EM) analysis using tools like RedHawk SC, Voltus.Define EM/IR methodologies and flows.Collaborate with design teams to improve power grid design and robustness.Ensure sign-off quality results for...

Key Responsibilities:Perform custom layout design of high-performance and low-power memory blocks (SRAM, ROM, Register Files, CAM, etc.).Work on floorplanning, transistor-level layout, device matching, and parasitic optimization.Ensure DRC/LVS clean layouts with adherence to foundry design rules.Collaborate with circuit design teams to achieve optimal PPA...

Responsibilities will include, but are not limited to: Ensure all the layout done and released from India team is as per quality guidelines, show continuous improvement in the quality of layout. Responsible for release of block on time as per the quality guidelines. Working experience in multiple silicon-proven tape-outs with multimillion gate count designs....

Job Description- Lead Netlist to-GDSII implementation, including floorplanning, power planning, placement, CTS, routing, and full signoff (DRC, LVS, STA, EMIR).- Own and drive PnR execution and closure at both block and top levels, addressing timing, congestion, IR-drop, and physical verification challenges.- Proficient with industry-standard tools: Cadence...

Company:ACL Digital CompanyLocation:BangaloreExperience:5 to 15 YearsEmployment Type:Full-TimeAre you passionate about Power Integrity, EM/IR signoff, and working on next-generation SoC designs?ACL Digital company, is looking for talented and drivenEMIR/PDN Engineersto be part of our world-class semiconductor design team inBangalore.Role &...

We are seeking an experienced Lead STA Engineer to take ownership of the static timing closure process for complex ASIC/SoC designs. In this role, you will lead timing sign-off activities, coordinate with cross-functional teams, and ensure designs meet performance, power, and area targets while achieving first-pass silicon success.Key Responsibilities:Own...

Key Skills: Static Timing Analysis,PrimeTimeRoles and Responsibilities:Conduct block-level and full-chip static timing analysis across all phases of development.Develop timing methodologies and infrastructure from RTL synthesis to timing closure.Collaborate with architects and designers to define block and chip-level timing constraints.Define analysis...