Senior Verification Engineer
3 days ago
Job Title: Senior Verification Engineer
Location: Bangalore, Hyderabad, Ahmedabad, Pune, Gurugram, Bhubaneswar
Experience: 5+ Years
Role Overview
We are seeking an experienced Senior Verification Engineer to join our dynamic team. The ideal candidate will bring strong expertise in UVM and SystemVerilog, with hands-on experience in verification of high-speed protocols and SoC/IP subsystems. This role requires deep technical knowledge, problem-solving ability, and collaboration with cross-functional engineering teams.
Key Responsibilities
- Develop and execute verification test plans using UVM methodology.
- Design and implement testbenches in SystemVerilog.
- Verify complex IPs, subsystems, and SoCs across multiple protocols.
- Debug, analyze, and resolve design and verification issues.
- Ensure functional coverage and contribute to verification closure.
- Collaborate closely with design, architecture, and validation teams.
Required Skills & Expertise
- Strong experience with UVM and SystemVerilog.
- Hands-on expertise in at least two or more of the following protocols:
- CXL, UCIe, PCIe, DDR, Ethernet, CHI
- Strong debugging and problem-solving skills.
- Solid understanding of verification methodologies, coverage-driven verification, and regression flows.
- Excellent communication and collaboration skills.
Job Types: Full-time, Permanent
Work Location: In person
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