DFT Lead Engineer
7 days ago
TITLE: DFT Lead Engineer
LOCATION: GREATER BENGALURU AREA
Company Description
With a strong focus on innovation and over two decades of experience, we deliver tailored AI-powered solutions across industries and global markets.
Job Description
- 8+yrs design experience
- Experience with owning chip level DFT and Post Silicon debug / analysis
- Understanding of DFT architectures like JTAG, Scan Compression Techniques (XOR, Adaptive, OP-MISR etc.), scan chain insertion and verification.
- Must have experience generating scan patterns and coverage statistics for various fault models like stuck at(Nominal and VBOX), IDDQ, Transition faults, JTAG BSDL, pattern generation for Memories(E-fuse etc.). Experience debugging tester failures of scan patterns, diagnosis and pattern re-generation.
- Understanding generation of functional patterns for ATE
- Knowledge of at least any one of an industry standard DFT tools (Cadence Modus, Synopsys Tetramax, Mentor Tessent Tools, etc)
- Design experience in MBIST / LBIST is an added advantage.
- Good understanding of constraints development for Physical Design Implementation / Static Timing Analysis.
- Preferred Skills/ Experience
- Experience with TCL / Perl is preferred.
- Understanding of IC design with Analog circuits and it's design cycles is an added advantage.
- Effective communication skills to interact with all stakeholders.
- Team and People Skills: The candidate should have good people skills to work closely with the systems, analog, layout and test team
- Must be highly focused and remain committed to obtaining closure on project goals
Contact
Sumit S. B
"Mining the Knowledge Community"
Practice Head(Talent Acquisition. Semiconductors Domain)
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