Lead Design Verification Engineer

4 days ago

Chennai, Tamil Nadu, India R2R Consultants Llp Full time ₹ 15,00,000 - ₹ 25,00,000 per year

Location : Chennai

Role & responsibilities :

Key Responsibilities:

  • Perform functional verification at block and chip level for complex ASIC/SoC designs.
  • Build UVM-based testbenches from scratch for new IPs or subsystems.
  • Develop and execute detailed verification test plans based on design specifications.
  • Write directed and constrained-random test cases; debug simulation failures.
  • Perform coverage analysis (functional and code) and drive closure.
  • Work with RAL (Register Abstraction Layer) to verify register-level functionality.
  • Develop and validate assertions (SVA) for protocol and functional correctness.
  • Collaborate closely with RTL, DFT, and GLS teams to ensure alignment across design phases.
  • Participate in multiple tapeouts, ensuring verification quality and delivery.

Key Skills :

  • Strong hands-on experience with SystemVerilog and UVM methodology.
  • Solid knowledge of SoC/ASIC architecture and verification lifecycle.
  • Hands-on experience in writing testbenches, stimulus, checkers, monitors, and scoreboards .
  • Strong debugging skills using simulation tools like VCS, Questa.
  • Experience with functional and code coverage.
  • Familiarity with Register Abstraction Layer (RAL) modeling and verification.
  • Excellent analytical and problem-solving skills.
  • Strong communication and teamwork abilities.
  • Education: B.E/B .Tech or M.E/M.Tech in Electronics, Electrical, or related fields.
  • Must have contributed to at least three or more successful tapeouts.

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