Memory Layout Engineer
8 hours ago
Industry experience in Memory Leafcell layout design
Strong understanding of memory architectures and performance optimization
Strong grasp of FinFET technology
Hands-on experience in memory domain: characterization, design, and validation
Proficient in writing Spice decks, stimulus, and test vectors
Experience with fast simulation tools and waveform vowere
Kriowledge of layout parasitic extraction and deep submicron technology challenges
Good at LVS/DRC debugging skills and other verifications for lower technology nodes
Familiar with EDA tools like Cadence SKILL scripting and automation for compiler Rows and layout reuse
Familiarity with NMDL + CCST libraries
Understanding layout effects on the circult such as speed, capacitance, power and area etc..
Capable of generating libs and performing QA sign-off
Ability to understand design constraints and implement high-quality layouts.
Good people siills and critical thinking abilities to resolve the issue technically, and professionally.
Minimum Educational Qualification: Educational Bachelor's, Electrical or Electronics Engineering or equivalent Rennirements
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