Radio Frequency Design Engineer

2 weeks ago

Bengaluru, Karnataka, India Best NanoTech Full time ₹ 12,00,000 - ₹ 36,00,000 per year

Job Title: Senior RF Design Engineer – PA/LNA/FEM ICs

Job Summary

We are looking for an experienced
Senior RF Design Engineer
with deep expertise in designing
Power Amplifiers (PAs), Low Noise Amplifiers (LNAs), and Front-End Module (FEM) ICs
across
X/Ku/Ka/E bands
. The role involves full-cycle RF design including simulation, layout, testing, and performance optimization.

Key Responsibilities

  • Design, simulate, and layout
    RF circuits
    including PAs, LNAs, and FEM ICs.
  • Perform
    electromagnetic (EM) simulations
    to validate design integrity.
  • Optimize circuits for
    efficiency, linearity, noise figure, gain, and bandwidth
    .
  • Develop
    test plans
    and conduct measurements using RF equipment (VNA, spectrum analyzer, power meters).
  • Debug and resolve RF performance issues across modules and subcircuits.
  • Collaborate with cross-functional teams for specification development and design reviews.
  • Document design methodologies, results, and test procedures.
  • Mentor junior engineers and contribute to continuous improvement in RF design practices.

Essential Qualifications

  • Bachelor's or Master's in Electrical/Electronics Engineering
    or related field.
  • 8–10+ years experience
    in RF circuit design, specifically PAs, LNAs, and FEM ICs.
  • Strong understanding of
    RF theory, transmission lines, S-parameters, stability, and impedance matching
    .
  • Proficiency in RF simulation tools such as
    Keysight ADS, AWR Microwave Office
    , or similar.
  • Hands-on experience with
    RF measurements, calibration techniques, and test equipment
    .
  • Knowledge of RF semiconductor processes (e.g.,
    GaN, GaAs, SiGe
    ).

Preferred Skills (Nice to Have)

  • Experience in
    antenna integration
    within FEM modules.
  • Familiarity with
    EM tools
    (HFSS, Momentum).
  • Knowledge of
    thermal modeling
    ,
    linearity enhancement techniques
    , or
    digital predistortion (DPD)
    .
  • Exposure to
    MMIC design
    and wafer-level testing.

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