Software Design Engineer in Test

7 days ago

Bengaluru, Karnataka, India NTek Software Solutions Full time ₹ 14,00,000 - ₹ 28,00,000 per year

Role - Design for Test (DFT) Engineer

Experience: 3+ Years

Client: TESSOLVE

Location: Bangalore

Budget: 4X times.

Required Technical and Professional Expertise:

Strong expertise in DFT architectures and methodologies, including but not limited to:

Scan Insertion & Verification

ATPG (Automatic Test Pattern Generation)

MBIST (Memory Built-In Self-Test)

JTAG / Boundary Scan

Hands-on experience with industry-standard DFT tools and methodologies from Cadence, Synopsys, and Mentor Graphics (Siemens EDA).

Proven ability to develop and debug scripting solutions using Python, Perl, and TCL for automation of DFT flows.

Solid understanding of SoC design cycle, RTL to GDSII flow, and test requirements.

Experience collaborating with RTL designers, verification engineers, and physical design teams to ensure seamless DFT integration.

Strong problem-solving skills, ability to debug complex test issues, and deliver high-quality DFT solutions within tight schedules.

Preferred Skills (Nice to Have)

Knowledge of low-power DFT techniques (power-aware ATPG, retention flops, etc.).

Experience with post-silicon bring-up and ATE patterns.

Familiarity with safety-critical standards (ISO 26262, DO-254, etc.).

Exposure to High-Speed IO testing (SERDES, DDR, etc.).

Responsibilities

Drive DFT architecture definition and implementation for complex SoCs.

Plan, execute, and deliver scan, ATPG, MBIST, and boundary scan insertion and validation.

Work with EDA vendors to evaluate, deploy, and optimize DFT tool flows.

Automate repetitive tasks using scripting to improve efficiency and reduce errors.

Support test vector generation and validation for ATE.

Provide technical guidance and mentorship to junior engineers in the DFT team.

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