Timing constraints leader

OUR STORY
At ST, we believe in the power of technology to drive innovation and make a positive impact on people, business, and society. We are a global semiconductor company, and our advanced technology & chips forms the hidden part of the world we live in today.

When you join ST, you will be part of a global business of more than 115+ nationalities and present in 40 countries, 50,000+, diverse and dedicated creators & makers of technology around the world

Developing technologies takes more than talent: it takes amazing people who understands collaboration and respect. People with passion and desire to disrupt the status quo, push boundaries and drive innovation – whilst unlocking your own potential.

Job Description
SoC constraints leader with extensive experience and proven track record in SoC/full-chip micro architecture and design with solid focus on delivering the products across various tech nodes. Individual should have very good hold on SoC global specs and functionalities like core, platforms, clock, reset & power, etc. Must have good understanding on adjoining SoC implementation functions like functional verification, DFT, physical implementation, timing analysis, pre & post-Si validation, test and product engineering etc.

The SoC constraints lead will be closely working and collaborating with systems teams and driving RTL design teams for specification development of IP's, complex subsystems, and chip-top, defining timign exceptions, timing definitions - taking the design from spec definition to RTL development and accordingly contraints development

Alongwith RTL, the candidate has also to ensure the collaterals related to timing constraints for the corresponding RTL, ensuring its formal/structural verification performed.

Responsibilities Include But Not Limited To
Drive architecture & application teams in converging to an optimal specification from performance, design effort/cost point of view. This includes detailed technical discussions and evaluations on IP choices and specifications, SoC architecture definitions covering different core and memory subsystems, solutions for clocking, power management, interconnect etc with target of PPA optimization to grant a competitive balance between product features and time-to-market.

Close engagement with systems teams and customer interfaces to enable correct design decisions while working to build and develop system level knowledge within the design team.

Conducts analyses covering feasibility studies, risk analysis, power, die size estimation etc.

Drive design implementation functions including sub-groups for RTL development and top integration, verification, performance evaluation and pre-Si validation, DFT, physical implementation team for execution of entire RTL2GDS flow.

Running weekly reviews of open issues across development functions, closely monitoring and tracking, and provide technical leadership to individuals from outside the function and owning the outcome of the project

Manage project-related activities like design team meetings, project status reporting, project reviews in compliance with product development lifecycle.

Collaborates with the teams across project core team members like engineering, validation, packaging, quality & reliability, marketing etc.

Technical Skills/background
Qualification: Bachelors/Masters in Electronics/Electrical Engineering

Experienced about system applications on aspects related to architectural choices in order to optimize for device performance, power and area.

Good knowledge and understanding of advanced ARM real time and application CPU cores and memory subsystems, system bus architectures (like AHB/AXI), Arteris NOC and other interconnect technologies, debug subsystems, critical aspects like SoC clocking, reset and power mgmt., high speed SerDes, analog integration, RTL design and SoC integration with multiple asynchronous clock domains, bottlenecks identification, timing issues anticipation and resolution.

Competent on power and clocking architectural concepts, capable of driving their definitions and anticipate potential implementation issues for high frequency designs.

Design experience in mid-high complexity product developments in FDSOI 28nm, 16 FFC, 7nm technology nodes.

Knowledge of Automotive Functional Safety ISO26262 is a plus.

Leadership Skills
Proven track record of leadership role in managing high level complex designs, driving and coordinating across different teams.

Good negotiator and able to manage tough situations.

Adaptability to align and balance resources & time constraints according to business need.

Should possess strong communication skills to ensure effective interaction both with Management and internal project/design sub-groups members

Good interpersonal skills.

Provide direction, mentoring, and leadership to small to medium-sized technical groups.

Working at ST means innovating for a future that we want to make smarter, greener, in a responsible and sustainable way. Our technology starts with you. Join us and start the future

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