Senior/Staff Engineer

1 day ago

Bengaluru, Karnataka, India Tenstorrent Full time ₹ 12,00,000 - ₹ 36,00,000 per year

Description :

Role : Senior/Staff Engineer, Physical Design (Clocking)

Job Summary :

Tenstorrent is seeking an experienced Senior/Staff Engineer, Physical Design (Clocking) to lead and own the critical clock design efforts across our cutting-edge IP, CPU, and SoC teams. This role demands 6 years of experience with a strong background in clock tree synthesis (CTS) and advanced clock network design. You will be responsible for defining comprehensive clocking strategies that achieve optimal balance across aggressive PPA (Power, Performance, Area) targets while ensuring robustness and high performance in complex AI systems, working in a highly collaborative, cross-functional environment.

Core Responsibilities :

Clock Architecture Ownership :

- Own the end-to-end clock architecture across complex SoCs, CPUs, and internal IP blocks.

- Define, architect, and implement clocking strategies that meet tight timing requirements, aggressive power goals, and constrained area targets.

- Ensure the clock network design is robust against variations and meets stringent jitter specifications.

Physical Design Implementation :

- Apply a strong technical background in clock tree synthesis (CTS) and the comprehensive clock network design process.

- Utilize expert knowledge of industry-standard tools like Synopsys Fusion Compiler (FC) and ICC2 for physical implementation and optimization.

- Work hands-on with advanced technology nodes (5nm or below), understanding how these nodes shape critical design choices related to clock distribution and PPA.

Analysis and Verification :

- Possess strong proficiency in analyzing and resolving complex issues related to timing closure, Clock Domain Crossing (CDC), and overall design functionality.

- Implement and verify low-power design techniques as they relate specifically to the clock network structure and overall system power reduction.

Cross-Functional Collaboration and Automation :

- Collaborate effectively with RTL, Physical Design (PD), and Power Engineers to ensure seamless integration and successful tape-out.

- Write robust scripts (using Python, Perl, or Tcl) to automate tasks, improve engineering workflows, and reduce manual effort in the clocking and physical design flow.

- Act as a problem-solver who thrives on making design flows more efficient, robust, and predictable.

Required Skills & Qualifications :

- Experience : 6 years of professional experience in Physical Design or Clocking.

- Clocking Expertise : Strong background in Clock Tree Synthesis (CTS) and comprehensive clock network design.

- Advanced Nodes : Proven experience working on advanced technology nodes (5nm or below).

- Tools : Proficiency with Synopsys tools such as Fusion Compiler (FC) and ICC2.

- Scripting : Strong scripting skills in Python, Perl, or Tcl for design automation and flow improvement.

- Verification : Comfortable working with complex timing, CDC, and low-power design techniques.

Preferred Skills :

- Direct experience leading the clock architecture definition for a complex CPU or high-performance SoC.

- Deep knowledge of jitter analysis and reduction techniques.

- Experience with power integrity issues related to the clock network.

Location & Logistics :

- Location : Onsite, based out of Bangalore.

- Experience : Candidates with 6 years of experience are welcomed.

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