SOC RTL Design Lead(SMTS)

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SMTS SILICON DESIGN ENGINEER
The Role
As a member of the Computing & Graphics (CG) SoC Architecture team, this SoC Power Management Design Engineer will develop and design custom silicon for gaming consoles, datacenter, client, or embedded computer vision SOCs and related platforms. In this role, you will work with the lead SoC architect to define customer-specific architectures and contribute to product specifications, micro-architecture specifications, performance and power trade-offs. The role will work from early concept development through the development phases to final production.

The Person
In this role, you will collaborate with a network of expert architects and designers around the world where collaboration and communication skills are critical to the success of this role, and excellent organization skills are essential. You will approach sophisticated problems with a firm methodology and problem-solving technique and conduct experiments and analysis to formulate recommendations and next steps for other colleagues and SOC and IP design teams located in across multiple time zones and geographies. You will formally present your findings to co-workers, teams, and customer engineering teams.

Key Responsiblities

• Drive the physical design, and power architecture based on customer-specific requirements
• Work with AMD's Engineering teams, and IP teams to help aid in their integration, implementation, and optimization of the designs through end-to-end documentation of flows etc.,
• Ability to understand power consumption and power delivery using combination of static, dynamic models, and emulation data
• Analyze performance across voltages for DVFS states of IPs, including inference engines, CPUs, Graphics, memory controllers, peripheral interfaces, caches and network-on-chip fabric
• Interacting with the technology teams, silicon validation, and product engineering teams to establish voltage-frequency design points
• Working with the systems and architecture team to evaluate and define definitions for on-die PDN, power gating, package, and system power delivery
• Analyze effects of control algorithms for management throttling mechanisms to achieve peak performance within thermal and peak current limits

Preferred Experience

• Solid understanding of SoC construction including fabric connectivity, memory systems, power delivery, clock distribution, floor planning, and packaging
• Strong understanding of SoC power management, power dissipation and mobile battery life
• Skills in scripting, data analysis, experience with EDA tools, physical design tools for power optimization, VLSI design flow and CMOS technology
• Ability to understand and model thermal control loops and throttling mechanisms
• Strong problem solving, organizational and communication skills, and ability to work in a dynamic and diverse environment
• Proficiency in scripting languages (Python) is highly preferred
• Experience with Power Architect, Power Artist and VisualSim a plus
• Detailed thinking skills. Ability deal with novel problems from different perspectives and from different levels of abstraction
• Ability to analyze and understand sophisticated workflows and processes, and develop innovative ways in streamlining and automating

Academic Credentials

• Bachelors or Masters degree in computer engineering/Electrical Engineering

Benefits offered are described:
AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.