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Analog Layout Engineer
2 weeks ago
Job Description
We are looking for a highly skilled Analog Layout Engineer to join our team in Bangalore. The ideal candidate should have strong hands-on experience in advanced CMOS technology nodes and be capable of working as an independent contributor.
- Experience in Cadence Virtuoso Layout Editor (XL), Cadence PVS & Calibre verification suite is mandatory.
- Good understanding of layout concepts like matching, shielding, latch up, EMIR, antenna effects, deep sub-micron effects, etc.
- Understanding and resolving LVS, DRC, DFM & Process related issues.
- Prior hands-on layout experience on power management analog circuits like amplifiers, comparators, LDOs, BGR's, ADC, DAC's, etc is added advantage.
- Higher planer process nodes experience is good.
- Should be an independent contributor.
Key Responsibilities:
- Perform full custom analog and mixed-signal layout design using Cadence Virtuoso Layout Editor (XL).
- Handle physical verification using Caliber / Cadence PVS (LVS, DRC, DFM).
- Ensure layout robustness for EM/IR, antenna, latch-up, shielding, matching, and other deep sub-micron effects.
- Debug and resolve process-related layout issues.
- Collaborate with circuit designers and verification teams to meet performance, area, and reliability requirements.
- Work on advanced technology nodes including TSMC 7nm, 12nm, 16nm, and 28nm.
Required Skills & Experience:
- 3 to 10 years of experience in Analog Layout Design.
Mandatory experience with:
Cadence Virtuoso Layout Editor (XL)
Calibre / Cadence PVS verification suite
Strong understanding of:
Matching techniques
- Shielding strategies
- EMIR, antenna effects, latch-up prevention
Deep sub-micron layout challenges
Proven experience in LVS, DRC, DFM closure.
- Experience with higher planar and advanced process nodes.
Preferred / Added Advantage:
Hands-on layout experience with Power Management & Analog Circuits such as:
Amplifiers
- Comparators
- LDOs
- Bandgap References (BGR)
ADCs / DACs
Experience working with or being deployed to Intel, Samsung, or similar Tier-1 semiconductor companies.
Other Requirements:
- Ability to work independently with minimal supervision.
- Strong problem-solving and debugging skills.
- Good communication and team collaboration skills.