Analog Layout Engineer
1 week ago
Your Profile:
We are seeking an experienced Analog Layout Design Engineer with strong expertise in advanced technology nodes and EDA tools. The role involves delivering high-quality analog layout designs at block/IP level, ensuring compliance with design rules and optimizing for performance, area, and reliability.
Key Responsibilities:
- Perform Analog Layout Design at Block/IP level for complex circuits.
- Execute LVS/DRC debugging and ensure design rule compliance.
- Work on FinFET technology nodes (5nm, 7nm, 10nm, 14nm and below).
- Utilize EDA tools for layout design and verification.
- Proficient in Cadence Virtuoso Editor for layout creation and optimization.
- Perform verification using Calibre RVE for LVS/DRC checks.
- Optimize layout for performance, area, and reliability.
- Conduct area estimation, floorplanning, and routing for analog blocks.
- Collaborate with circuit designers to meet design specifications and timelines.
Required Skills & Expertise:
- Strong knowledge of Analog Layout Design principles.
- Hands-on experience with FinFET nodes (5nm and below preferred).
- Proficiency in Cadence Virtuoso, Calibre RVE, and other EDA tools.
- Expertise in LVS/DRC debugging and layout optimization techniques.
- Good understanding of floorplanning, routing, and area estimation.
- Ability to work in a fast-paced environment and deliver high-quality results.
Preferred Qualifications:
- Experience in advanced technology nodes beyond 5nm.
- Familiarity with mixed-signal layout design.
- Strong problem-solving and analytical skills.
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