Asic - Fpga Design and Verification

1 week ago

Bengaluru, India Rapid Global Business Solutions Full time

**Basic Qualifications (Required Skills/Experience)**:

- Bachelor, Master or Doctorate of Science degree from an accredited course of study, in engineering, computer science, mathematics, physics or chemistry
- 8 or more years' of experience in Digital ASIC design and verification.
- Work experience using VHDL, Verliog or SystemVerilog.

**Preferred Qualifications (Desired Skills/Experience)**:

- Bachelor's degree and 8 or more years' experience in digital ASIC/FPGA design and verification, Master's degree with 6 or more years' experience in digital design/verification, or PhD degree with relevant years of experience in digital design/verification.
- design of RTL code from requirements, reporting status to program management.
- Experience working other engineering teams (e.g. board designers, system engineers, requirement engineers, reliability engineers, engineers), to ensure the ASIC/FPGA functions safely and reliably when deployed by assisting in Worst Case Circuit Analysis, IO timing, IO type selection, life analysis, software con-ops, MTBF analysis, etc.
- Experience creating and improving department process guidelines and procedures (e.g. engineering standards, checklists, process flows, etc.).
- Experience evaluating and recommending technology that is new to the organization.
- Experience leading development of architectural approaches from customer and system requirements.
- Experience designing digital ASIC/FPGA architectural design documents (micro-architecture documents with timing diagrams, detailed design blocks, etc.).
- Experience deriving digital ASIC/FPGA requirements specification from higher-level (system or board-level) requirements specifications.
- Experience identifying, tracking, and providing status of technical performance metrics to measure progress and ensure compliance with requirements.
- Experience in developing complex and high data rate designs.
- Experience performing RTL synthesis.
- Experience performing clock cross domain analysis (CDC).
- Work experience performing Static Timing Analysis and correcting timing violations.
- Work experience writing Universal Verification Methodology (UVM) sequences and virtual sequences.
- Work experience using Linux or Unix terminal commands.

**o Experience using scripting languages**: Make, Perl, Python, shell scripts, etc.

**o Experience using Revision Control Systems**: Subversion (SVN), CVS, Git.
- Work experience simulating a digital design using SystemVerilog Assertions.

**o Work experience using Object Oriented Programming concepts**: Inheritance, Polymorphism, etc.
- Work experience using Universal Verification Methodology (UVM): Experience creating drivers, monitors, predictors, and scoreboards.
- Experience on Digital interfaces such as LDVS, Spacewire, Fiber Channel, RS422, MIL1553, SRIO, Audio Video Interfaces, Ethernet, PCIe Gen3 and above.
- Work experience creating a self-checking simulation testbench from scratch.
- Experience mentoring junior engineers.
- Experience in establishing and rigorously implementing processes such as DO254, MIL-STD-882E an MIL-HDBK-516 or equivalent industry standards for commercial platforms

**Typical Education & Experience**:
Education/experience typically acquired through advanced education (e.g. Bachelor) and typically 8-10 years of related work experience or an equivalent combination of education and experience (e.g. Master 6+ years' related work experience, etc.).

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