Asic Verification

6 days ago

Bengaluru, India Creencia Full time

**Job Description for Design Verification**

**Responsibilities**:

- You will be exposed to the latest verification methodologies like UVM and enable complex feature verification suites.
- Architect and Develop block level verification environments for sub-system and fullchip using System Verilog and UVM methodology.
- Define, architect, code, and deliver verification suites/tests for ASICs that enable faster, denser, feature-rich systems. Use various front-end simulator tools (VCS/NC) to perform this activity.
- Verify large ASIC blocks independently and rapidly and sign off them for tape-out with analysis of code coverage, functional coverage and Gate level simulation.
- Develop Perl, Python and/or shell scripts to improve current verification infrastructure/methodology

**Required Skills**:

- ASIC Verification using SystemVerilog
- Experience in constrained-random verification is a strong plus
- Experience with verification methodology like OVM/VMM/UVM
- Perl/Tcl scripting is strongly preferred
- Strong problem-solving and ASIC debugging skills

**Salary**: ₹150,000.00 - ₹250,000.00 per year

Schedule:

- Day shift

Ability to commute/relocate:

- Bangalore, Karnataka: Reliably commute or planning to relocate before starting work (required)

Application Question(s):

- How many Years of experience do you have in ASIC verification?
- How many projects have you handled for ASIC verification?

**Experience**:

- total work: 6 years (preferred)

**Speak with the employer**

+91-XXXXXXXXXX

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