
Asic Verification
6 days ago
**Tasks**:
- Verification SoCs, automotive ASICs, subsystems, IPs.
- Application of Metric-driven Verification (MDV) and/or Formal Verification methodologies
- Developing and tracking of Verification plans
- Develop verification environments from scratch
- Create VIP
- Integration of VIP („Verification-IP“)
- Measure and analyze regression results
- Continuous improvement of verification methods/tools/flows/processes together with EDA partners
**Requirement**:
- 5 to 8 years of hands on Experience in RTL verification using SV and UVM.
- Must have been a part of one or more ASIC/SoC tape outs.
- Knowledge of VHDL/VERILOG.
- Sound knowledge of constrained random verification, OVM/UVM
- Sound knowledge in SV.
- Experience of developing functional coverage code, coverage analysis.
- Experience of developing verification environments from scratch is desirable.
- Formal verification experience is a desirable but not must.
- SPECMAN knowledge is a desirable but not must.
- Good hands on experience with cadence/Synopsys/Mentor tools.
- Exposure to configuration management, bug tracking tool etc.
- Knowledge of scripting language, Perl TCL etc.
- Good experience with AMBA protocols
- Working knowledge on ARM processor based subsystem/SoC verification
**Qualifications**
BE / B.Tech/M Tech (ECE)
**Salary**: Up to ₹3,500,000.00 per year
**Benefits**:
- Health insurance
Schedule:
- Day shift
Supplemental pay types:
- Joining bonus
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